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Re: ARM patch: Split compare_scc (PR42835)
- From: Bernd Schmidt <bernds at codesourcery dot com>
- To: Richard Earnshaw <rearnsha at arm dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Sat, 03 Jul 2010 13:46:25 +0200
- Subject: Re: ARM patch: Split compare_scc (PR42835)
- References: <4BC83E47.firstname.lastname@example.org> <email@example.com>
On 07/01/2010 03:38 PM, Richard Earnshaw wrote:
> This is OK.
> Note that there are several store-flag sequences that don't need
> conditional execution at all. For example:
> r = (a == b)
> sub t1, a, b
> rsbs r, t1, #0 @(negs), C=1 => t1 == 0
> adc r, r, t1 @ t1 + -t1 + C
> On Thumb-2 that's likely to be more efficient than the moveq/movne
> sequence which requires 4 insns once you include the IT insn (but
> doesn't need a scratch reg). The above sequence can also be used on
> Thumb-1 (since the first and third instructions can safely clobber the
I've played with this a little; see the patch below. Note that I
haven't tested whether it's faster this way.
Beside adding the peephole, this clears up some oddities elsewhere.
There were several adc patterns with noncanonical RTL (plus inside plus
not the first operand). Now that we have a CC_NOTB code, I've added a
code_iterator to enable adc to use that as well. Also, the subsi3
pattern didn't allow all the operand combinations supported by the
machine. These are changes I also need for other work, so it would be
nice if they were approved quickly so I don't have to submit them with
Tested with my usual set of multilibs on QEMU arm-linux. Ok?