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Re: RFC: PR rtl-optimization/44695: [4.6 Regression] ice in simplify_subreg, at simplify-rtx.c:5117
Why isn't HImode on operand 1 OK?
Because modes don't match between the div and its operands.
My comment in the PR is based on how GCC handles extension of the
dividend for 16/32/64 bit operands.
Your suggestion generate a pattern unsupported by hardware
That's what 16/32/64 bit operands do too
[(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
(match_operand:SWIM248 1 "register_operand" "")
(match_operand:SWIM248 2 "nonimmediate_operand" "")))
(set (match_operand:SWIM248 3 "register_operand" "")
(mod:SWIM248 (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
and introduces an extra register move during split to fix it.
I think you mean one extra extension? That's possible, though it could
be fixed in combine using nonzero_bits or num_sign_bit_copies.
Anyway, can you please post the patch and the result? I think you
should go one step at a time and first fix this bug, then optimize it.