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Re: [PATCH, ARM] Low interrupt latency support (avoiding ldm/stm)
Paul Brook wrote:
>> Additionally, cores without caches normally perform ldm/stm much more
>> efficiently than individual loads, so it can cost significant extra
>> overall time in that case.
>
> I believe it was LDM/STM specifically that motivated this change. IIUC the
> third party cores effectively microcode these.
That matches my understanding as well. In the context of the cores in
question, the assumption is that there is a lot of memory available, but
that failing to handle interrupts quickly is very bad, and that LDM/STM
are always slower than individual loads and stores. I don't understand
why we should not have an option to completely disable LDM/STM, given
that on this silicon it is apparently always a lose.
That's not to say that the RealView approach wouldn't also be a good
idea, but it seems reasonable to me to get this patch in, given that
even if we did implement the RealView approach it wouldn't be optimal on
the cores in question.
--
Mark Mitchell
CodeSourcery
mark@codesourcery.com
(650) 331-3385 x713