Re: [PATCH, ARM] Low interrupt latency support (avoiding ldm/stm)

[Julian Brown <julian at codesourcery dot com>]

On Thu, 20 May 2010 13:19:45 +0100
Julian Brown <julian@codesourcery.com> wrote:

> On Tue, 18 May 2010 11:49:17 +0100
> Paul Brook <paul@codesourcery.com> wrote:
> 
> > > > It appears the feature I was thinking of[1] was only
> > > > standardised in ARMv6, and may not be present on earlier cores.
> > > > It's definitely present on arm11 and cortex-a8/r4/m3 based
> > > > cores.
> > > 
> > > OK, so Paul, where does that leave us?  If Phil is right that this
> > > is in fact pretty universal (and not unique to Marvell Feroceon
> > > for which this patch was originally developed, IIRC), do you still
> > > object to it going in?  (I have no opinion the name; if you prefer
> > > -mavoid-ldm, that seems OK, though of course it also applies to
> > > STM.)
> > 
> > I think the documentation needs improving. i.e. explain when it
> > should be used and, more importantly, when it provides no benefit
> > (Cortex-M[34], most armv6+ cores in low latency mode). Other than
> > that it looks ok.  I don't care enough to argue about the name.
> 
> Here's a new version of the patch. I've renamed the option
> "-mmultiple" for slight consistency with other targets and reversed
> the sense (i.e. it is enabled by default, and you should use
> "-mno-multiple" to turn off ldm/stm instructions). I've also improved
> the documentation somewhat.
> 
> I'm not entirely sure still whether applying this patch is a good idea
> though. There's a lot of potential for bit-rot to creep in (i.e.
> introduction of ldm/stm or fldm/fstm instructions without checking the
> use_load_store_multiple flag). OTOH I believe ARM's own compiler has
> supported a similar option since prehistoric times, so maybe there's
> demand.
> 
> Richard, what do you think?

Ping (Richard)?

Julian