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Re: [PATCH, ARM] Low interrupt latency support (avoiding ldm/stm)
- From: Paul Brook <paul at codesourcery dot com>
- To: Phil Blundell <philb at gnu dot org>
- Cc: gcc-patches at gcc dot gnu dot org, Julian Brown <julian at codesourcery dot com>, rearnsha at arm dot com
- Date: Mon, 17 May 2010 13:27:38 +0100
- Subject: Re: [PATCH, ARM] Low interrupt latency support (avoiding ldm/stm)
- References: <20091127175025.7fb6ceae@rex.config> <201005171211.13307.paul@codesourcery.com> <1274097979.18119.835.camel@mill.internal.reciva.com>
> On Mon, 2010-05-17 at 12:11 +0100, Paul Brook wrote:
> > My understanding is that this option is only useful is only really useful
> > useful on certain third party cores, none of which are supported by FSF
> > gcc. I'd also guess that future (or even present) cores will have a
> > different criteria for generating "low-latency" code.
>
> I'm fairly sure that LDM and STM are uninterruptible instructions on
> most/all current cores, both ARM's own and those from third parties. An
> instruction like "stmia r0, {r0-r15}" will take at least 16 cycles on
> most processors and interrupts are locked out for the duration.
>
> To take a random-ish example, see the ARM9EJ-S reference manual:
> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0222b/CHDCBECF.html
It appears the feature I was thinking of[1] was only standardised in ARMv6,
and may not be present on earlier cores. It's definitely present on arm11 and
cortex-a8/r4/m3 based cores.
Paul
[1] cp15,c1 Bit 21 "Fast interrupt"