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[vect256] PATCH: Fix vec_unpacks_hi_v8sf/vec_unpacks_float_hi_v8si
- From: "H.J. Lu" <hongjiu dot lu at intel dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard Guenther <rguenther at suse dot de>
- Date: Fri, 14 May 2010 14:14:02 -0700
- Subject: [vect256] PATCH: Fix vec_unpacks_hi_v8sf/vec_unpacks_float_hi_v8si
- Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>
Hi,
vec_unpacks_hi_v8sf and vec_unpacks_float_hi_v8si are wrong.
They should convert the high 4 elements to V4DF. I am checking
this patch. Also I added *avx_cvtdq2pd256_2. As for
*avx_cvtps2pd256_2, it is OK to load the first 128bit memory
from a 256bit memory location. Checked into vect256 branch.
H.J.
---
diff --git a/gcc/ChangeLog.vect256 b/gcc/ChangeLog.vect256
index 06dcb1d..da97ee9 100644
--- a/gcc/ChangeLog.vect256
+++ b/gcc/ChangeLog.vect256
@@ -1,5 +1,12 @@
2010-05-14 H.J. Lu <hongjiu.lu@intel.com>
+ * config/i386/sse.md (*avx_cvtdq2pd256_2): New.
+ (*avx_cvtps2pd256_2): Allow memory source.
+ (vec_unpacks_hi_v8sf): Fixed.
+ (vec_unpacks_float_hi_v8si): Likewise.
+
+2010-05-14 H.J. Lu <hongjiu.lu@intel.com>
+
PR middle-end/44144
* tree-vect-data-refs.c (vect_create_data_ref_ptr): Increase
base_name alignment only if base_name is a variable.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a953c50..774b1b9 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2959,6 +2959,18 @@
(set_attr "prefix" "vex")
(set_attr "mode" "V4DF")])
+(define_insn "*avx_cvtdq2pd256_2"
+ [(set (match_operand:V4DF 0 "register_operand" "=x")
+ (float:V4DF
+ (vec_select:V4SI
+ (match_operand:V8SI 1 "nonimmediate_operand" "xm")
+ (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))]
+ "TARGET_AVX"
+ "vcvtdq2pd\t{%x1, %0|%0, %x1}"
+ [(set_attr "type" "ssecvt")
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "V4DF")])
+
(define_insn "sse2_cvtdq2pd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(float:V2DF
@@ -3143,7 +3155,7 @@
[(set (match_operand:V4DF 0 "register_operand" "=x")
(float_extend:V4DF
(vec_select:V4SF
- (match_operand:V8SF 1 "nonimmediate_operand" "x")
+ (match_operand:V8SF 1 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))]
"TARGET_AVX"
"vcvtps2pd\t{%x1, %0|%0, %x1}"
@@ -3187,26 +3199,18 @@
(define_expand "vec_unpacks_hi_v8sf"
[(set (match_dup 2)
- (vec_select:V8SF
- (vec_concat:V16SF
- (match_dup 2)
- (match_operand:V8SF 1 "nonimmediate_operand" ""))
- (parallel [(const_int 12)
- (const_int 13)
- (const_int 14)
- (const_int 15)
- (const_int 4)
- (const_int 5)
- (const_int 6)
- (const_int 7)])))
- (set (match_operand:V4DF 0 "register_operand" "")
- (float_extend:V4DF
- (vec_select:V4SF
- (match_dup 2)
- (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))]
- "TARGET_AVX"
+ (vec_select:V4SF
+ (match_operand:V8SF 1 "nonimmediate_operand" "")
+ (parallel [(const_int 4)
+ (const_int 5)
+ (const_int 6)
+ (const_int 7)])))
+ (set (match_operand:V4DF 0 "register_operand" "")
+ (float_extend:V4DF
+ (match_dup 2)))]
+ "TARGET_AVX"
{
- operands[2] = gen_reg_rtx (V8SFmode);
+ operands[2] = gen_reg_rtx (V4SFmode);
})
(define_expand "vec_unpacks_lo_v4sf"
@@ -3299,23 +3303,17 @@
(define_expand "vec_unpacks_float_hi_v8si"
[(set (match_dup 2)
- (vec_select:V8SI
- (match_operand:V4SI 1 "nonimmediate_operand" "")
+ (vec_select:V4SI
+ (match_operand:V8SI 1 "nonimmediate_operand" "")
(parallel [(const_int 4)
(const_int 5)
(const_int 6)
- (const_int 7)
- (const_int 4)
- (const_int 5)
- (const_int 6)
(const_int 7)])))
(set (match_operand:V4DF 0 "register_operand" "")
(float:V4DF
- (vec_select:V4SI
- (match_dup 2)
- (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))]
- "TARGET_AVX"
- "operands[2] = gen_reg_rtx (V8SImode);")
+ (match_dup 2)))]
+ "TARGET_AVX"
+ "operands[2] = gen_reg_rtx (V4SImode);")
(define_expand "vec_unpacks_float_lo_v8si"
[(set (match_operand:V4DF 0 "register_operand" "")