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[Committed] S/390: Support 32-bit applications using 64-bit register set on s390x-linux
- From: "Andreas Krebbel" <krebbel at linux dot vnet dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 13 Apr 2010 11:15:52 +0200
- Subject: [Committed] S/390: Support 32-bit applications using 64-bit register set on s390x-linux
Hi,
the attached patch enables the S/390 back-end to make use of 64 bit
registers when compiling 32 bit code. This is possible if the 32 bit
code is known to run always on a 64 bit kernel. The new mode is
enabled when compiling with -m31 -mzarch. The -mzarch switch builds
for machines where the z/Architecture mode is enabled and in that mode
the 64 bit registers are available.
In order to make this work the kernel has to save and restore the
upper halfs of 64 bit registers even when running just 32 bit code.
Kernels starting with version 2.6.32 already support this and indicate
the fact in /proc/cpuinfo as "highgprs" and in the AT_HWCAPS field of
the auxiliary vector with the HWCAP_S390_HIGH_GPRS flag.
In order to prevent new -m31 -mzarch executables and DSOs to be run on
an kernel not saving the upper halfs of the registers I have added a
runtime check into the glibc startup code:
http://sources.redhat.com/ml/libc-alpha/2010-01/msg00033.html
A binutils patch makes sure that executables compiled with -m31
-mzarch are marked to require the kernel feature:
http://sourceware.org/ml/binutils/2010-01/msg00373.html
And last but not least Ulrich took care of the GDB support:
http://sourceware.org/ml/gdb-patches/2009-12/msg00303.html
Committed to mainline.
Bye,
-Andreas-
2010-04-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH.
* gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with
UNITS_PER_LONG where it is ABI relevant.
(s390_return_addr_rtx): Likewise.
(s390_back_chain_rtx): Likewise.
(s390_frame_area): Likewise.
(s390_frame_info): Likewise.
(s390_initial_elimination_offset): Likewise.
(save_gprs): Likewise.
(s390_emit_prologue): Likewise.
(s390_emit_epilogue): Likewise.
(s390_function_arg_advance): Likewise.
(s390_function_arg): Likewise.
(s390_va_start): Likewise.
(s390_gimplify_va_arg): Likewise.
(s390_function_profiler): Likewise.
(s390_optimize_prologue): Likewise.
(s390_rtx_costs): Likewise.
(s390_secondary_reload): Likewise.
(s390_promote_function_mode): Likewise.
(s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH.
(s390_scalar_mode_supported_p): Disallow TImode if no 64 bit
registers available.
(s390_unwind_word_mode): New function.
(s390_function_value): Split 64 bit values into register pair if
used as return value.
(s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for
function call parameters. Handle parallels.
(TARGET_SCALAR_MODE_SUPPORTED_P): New macro.
(HARD_REGNO_CALL_PART_CLOBBERED): New macro.
(DWARF_CIE_DATA_ALIGNMENT): New macro.
(s390_expand_setmem): Remove unused variable src_addr.
* gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to
deal with 64 bit registers.
* gcc/config/s390/s390.h: Define __zarch__ predefined macro.
Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant.
(UNITS_PER_LONG): New macro.
* libjava/include/s390-signal.h: Define extended ucontext
structure containing the upper halfs of the 64 bit registers.
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 337,357 ****
;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
;; from the same template.
! (define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
(define_mode_iterator DSI [DI SI])
;; These mode iterators allow :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
- (define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
;; This mode iterator allows the QI and HI patterns to be defined from
;; the same template.
(define_mode_iterator HQI [HI QI])
;; This mode iterator allows the integer patterns to be defined from the
;; same template.
! (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
(define_mode_iterator INTALL [TI DI SI HI QI])
;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
--- 337,361 ----
;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
;; from the same template.
! (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
(define_mode_iterator DSI [DI SI])
;; These mode iterators allow :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
+ ;; These macros refer to the actual word_mode of the configuration. This is equal
+ ;; to Pmode except on 31-bit machines in zarch mode.
+ (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
+ (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
+
;; This mode iterator allows the QI and HI patterns to be defined from
;; the same template.
(define_mode_iterator HQI [HI QI])
;; This mode iterator allows the integer patterns to be defined from the
;; same template.
! (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
(define_mode_iterator INTALL [TI DI SI HI QI])
;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
***************
*** 455,461 ****
;; variant for long displacements.
(define_mode_attr y [(DI "g") (SI "y")])
! ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
;; and "cds" in DImode.
(define_mode_attr tg [(TI "g") (DI "")])
--- 459,465 ----
;; variant for long displacements.
(define_mode_attr y [(DI "g") (SI "y")])
! ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
;; and "cds" in DImode.
(define_mode_attr tg [(TI "g") (DI "")])
***************
*** 506,512 ****
(match_operand:DI 1 "immediate_operand"
"N0HD0,N1HD0,N2HD0,N3HD0"))
(match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
! "TARGET_64BIT
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
&& s390_single_part (operands[1], DImode, HImode, 0) >= 0"
"@
--- 510,516 ----
(match_operand:DI 1 "immediate_operand"
"N0HD0,N1HD0,N2HD0,N3HD0"))
(match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
! "TARGET_ZARCH
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
&& s390_single_part (operands[1], DImode, HImode, 0) >= 0"
"@
***************
*** 556,562 ****
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d,d")
(sign_extend:DI (match_dup 0)))]
! "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"ltgfr\t%2,%0
ltgf\t%2,%0"
[(set_attr "op_type" "RRE,RXY")
--- 560,566 ----
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d,d")
(sign_extend:DI (match_dup 0)))]
! "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
"ltgfr\t%2,%0
ltgf\t%2,%0"
[(set_attr "op_type" "RRE,RXY")
***************
*** 596,602 ****
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d")
(match_dup 0))]
! "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
"ltgr\t%2,%0"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_fr_E1")])
--- 600,606 ----
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d")
(match_dup 0))]
! "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
"ltgr\t%2,%0"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_fr_E1")])
***************
*** 632,638 ****
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
! "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
"srda\t%0,0"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 636,642 ----
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
! "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
"srda\t%0,0"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
***************
*** 720,726 ****
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
(match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
! "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
"@
cgr\t%0,%1
cghi\t%0,%h1
--- 724,730 ----
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
(match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
! "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
"@
cgr\t%0,%1
cghi\t%0,%h1
***************
*** 752,758 ****
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))]
! "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
"@
cgfr\t%0,%1
cgf\t%0,%1
--- 756,762 ----
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))]
! "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
"@
cgfr\t%0,%1
cgf\t%0,%1
***************
*** 847,853 ****
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))]
! "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
"@
clgfr\t%0,%1
clgf\t%0,%1
--- 851,857 ----
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))]
! "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
"@
clgfr\t%0,%1
clgf\t%0,%1
***************
*** 863,869 ****
"d, d,d,Q, d, Q,BQ")
(match_operand:DI 1 "general_operand"
"d,Op,b,D,RT,BQ,Q")))]
! "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
"@
clgr\t%0,%1
clgfi\t%0,%1
--- 867,873 ----
"d, d,d,Q, d, Q,BQ")
(match_operand:DI 1 "general_operand"
"d,Op,b,D,RT,BQ,Q")))]
! "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
"@
clgr\t%0,%1
clgfi\t%0,%1
***************
*** 1115,1121 ****
(define_insn "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
(match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
! "TARGET_64BIT"
"@
lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0
--- 1119,1125 ----
(define_insn "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
(match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
! "TARGET_ZARCH"
"@
lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0
***************
*** 1127,1133 ****
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
! "TARGET_64BIT && reload_completed
&& s390_split_ok_p (operands[0], operands[1], TImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
--- 1131,1137 ----
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
! "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], TImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
***************
*** 1141,1147 ****
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
! "TARGET_64BIT && reload_completed
&& s390_split_ok_p (operands[0], operands[1], TImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
--- 1145,1151 ----
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
! "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], TImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
***************
*** 1155,1165 ****
(define_split
[(set (match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "memory_operand" ""))]
! "TARGET_64BIT && reload_completed
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
{
rtx addr = operand_subword (operands[0], 1, 0, TImode);
s390_load_address (addr, XEXP (operands[1], 0));
operands[1] = replace_equiv_address (operands[1], addr);
})
--- 1159,1170 ----
(define_split
[(set (match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "memory_operand" ""))]
! "TARGET_ZARCH && reload_completed
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
{
rtx addr = operand_subword (operands[0], 1, 0, TImode);
+ addr = gen_lowpart (Pmode, addr);
s390_load_address (addr, XEXP (operands[1], 0));
operands[1] = replace_equiv_address (operands[1], addr);
})
***************
*** 1308,1314 ****
(match_operand:DI 1 "general_operand"
"K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
! "TARGET_64BIT"
"@
lghi\t%0,%h1
llihh\t%0,%i1
--- 1313,1319 ----
(match_operand:DI 1 "general_operand"
"K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
! "TARGET_ZARCH"
"@
lghi\t%0,%h1
llihh\t%0,%i1
***************
*** 1375,1381 ****
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
! "TARGET_64BIT && ACCESS_REG_P (operands[1])"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
(set (strict_low_part (match_dup 2)) (match_dup 4))]
--- 1380,1386 ----
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
! "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
(set (strict_low_part (match_dup 2)) (match_dup 4))]
***************
*** 1385,1391 ****
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
! "TARGET_64BIT && ACCESS_REG_P (operands[0])
&& dead_or_set_p (insn, operands[1])"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
--- 1390,1396 ----
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
! "TARGET_ZARCH && ACCESS_REG_P (operands[0])
&& dead_or_set_p (insn, operands[1])"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
***************
*** 1396,1402 ****
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
! "TARGET_64BIT && ACCESS_REG_P (operands[0])
&& !dead_or_set_p (insn, operands[1])"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
--- 1401,1407 ----
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
! "TARGET_ZARCH && ACCESS_REG_P (operands[0])
&& !dead_or_set_p (insn, operands[1])"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
***************
*** 1410,1416 ****
"=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
(match_operand:DI 1 "general_operand"
" Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
! "!TARGET_64BIT"
"@
lm\t%0,%N0,%S1
lmy\t%0,%N0,%S1
--- 1415,1421 ----
"=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
(match_operand:DI 1 "general_operand"
" Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
! "!TARGET_ZARCH"
"@
lm\t%0,%N0,%S1
lmy\t%0,%N0,%S1
***************
*** 1433,1439 ****
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))]
! "!TARGET_64BIT && reload_completed && TARGET_Z10
&& larl_operand (XEXP (operands[1], 0), SImode)"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0) (match_dup 1))]
--- 1438,1444 ----
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))]
! "!TARGET_ZARCH && reload_completed && TARGET_Z10
&& larl_operand (XEXP (operands[1], 0), SImode)"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0) (match_dup 1))]
***************
*** 1446,1452 ****
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
! "!TARGET_64BIT && reload_completed
&& s390_split_ok_p (operands[0], operands[1], DImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
--- 1451,1457 ----
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
! "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], DImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
***************
*** 1460,1466 ****
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
! "!TARGET_64BIT && reload_completed
&& s390_split_ok_p (operands[0], operands[1], DImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
--- 1465,1471 ----
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
! "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], DImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
***************
*** 1474,1480 ****
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))]
! "!TARGET_64BIT && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
--- 1479,1485 ----
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))]
! "!TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
***************
*** 1487,1493 ****
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(mem:DI (match_operand 1 "address_operand" "")))]
! "TARGET_64BIT
&& !FP_REG_P (operands[0])
&& GET_CODE (operands[1]) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (operands[1])
--- 1492,1498 ----
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(mem:DI (match_operand 1 "address_operand" "")))]
! "TARGET_ZARCH
&& !FP_REG_P (operands[0])
&& GET_CODE (operands[1]) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (operands[1])
***************
*** 1826,1833 ****
&& register_operand (operands[0], VOIDmode)
&& GET_CODE (operands[1]) == MEM)
{
! rtx tmp = gen_reg_rtx (word_mode);
! rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
operands[1] = gen_lowpart (QImode, tmp);
}
--- 1831,1838 ----
&& register_operand (operands[0], VOIDmode)
&& GET_CODE (operands[1]) == MEM)
{
! rtx tmp = gen_reg_rtx (DImode);
! rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
operands[1] = gen_lowpart (QImode, tmp);
}
***************
*** 1905,1911 ****
(define_insn "movstrictsi"
[(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
(match_operand:SI 1 "general_operand" "d,R,T,t"))]
! "TARGET_64BIT"
"@
lr\t%0,%1
l\t%0,%1
--- 1910,1916 ----
(define_insn "movstrictsi"
[(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
(match_operand:SI 1 "general_operand" "d,R,T,t"))]
! "TARGET_ZARCH"
"@
lr\t%0,%1
l\t%0,%1
***************
*** 1928,1934 ****
(define_insn "*mov<mode>_64"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
! "TARGET_64BIT"
"@
lzxr\t%0
lxr\t%0,%1
--- 1933,1939 ----
(define_insn "*mov<mode>_64"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
! "TARGET_ZARCH"
"@
lzxr\t%0
lxr\t%0,%1
***************
*** 1944,1950 ****
(define_insn "*mov<mode>_31"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
! "!TARGET_64BIT"
"@
lzxr\t%0
lxr\t%0,%1
--- 1949,1955 ----
(define_insn "*mov<mode>_31"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
! "!TARGET_ZARCH"
"@
lzxr\t%0
lxr\t%0,%1
***************
*** 1958,1964 ****
(define_split
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
! "TARGET_64BIT && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
--- 1963,1969 ----
(define_split
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
! "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
***************
*** 1972,1978 ****
(define_split
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
! "TARGET_64BIT && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
--- 1977,1983 ----
(define_split
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
! "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
***************
*** 1986,1992 ****
(define_split
[(set (match_operand:TD_TF 0 "register_operand" "")
(match_operand:TD_TF 1 "memory_operand" ""))]
! "TARGET_64BIT && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
--- 1991,1997 ----
(define_split
[(set (match_operand:TD_TF 0 "register_operand" "")
(match_operand:TD_TF 1 "memory_operand" ""))]
! "TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
***************
*** 2045,2051 ****
"=f,f,f,d,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand"
" G,f,d,f,R,T,f,f,d,RT, d"))]
! "TARGET_64BIT && TARGET_DFP"
"@
lzdr\t%0
ldr\t%0,%1
--- 2050,2056 ----
"=f,f,f,d,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand"
" G,f,d,f,R,T,f,f,d,RT, d"))]
! "TARGET_DFP"
"@
lzdr\t%0
ldr\t%0,%1
***************
*** 2077,2083 ****
(define_insn "*mov<mode>_64"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
! "TARGET_64BIT"
"@
lzdr\t%0
ldr\t%0,%1
--- 2082,2088 ----
(define_insn "*mov<mode>_64"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
! "TARGET_ZARCH"
"@
lzdr\t%0
ldr\t%0,%1
***************
*** 2106,2112 ****
"=f,f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand"
" G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
! "!TARGET_64BIT"
"@
lzdr\t%0
ldr\t%0,%1
--- 2111,2117 ----
"=f,f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand"
" G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
! "!TARGET_ZARCH"
"@
lzdr\t%0
ldr\t%0,%1
***************
*** 2127,2133 ****
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
! "!TARGET_64BIT && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
--- 2132,2138 ----
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
! "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
***************
*** 2141,2147 ****
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
! "!TARGET_64BIT && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
--- 2146,2152 ----
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
! "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
***************
*** 2155,2161 ****
(define_split
[(set (match_operand:DD_DF 0 "register_operand" "")
(match_operand:DD_DF 1 "memory_operand" ""))]
! "!TARGET_64BIT && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
--- 2160,2166 ----
(define_split
[(set (match_operand:DD_DF 0 "register_operand" "")
(match_operand:DD_DF 1 "memory_operand" ""))]
! "!TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
***************
*** 2304,2310 ****
count = INTVAL (operands[2]);
regno = REGNO (operands[0]);
mode = GET_MODE (operands[0]);
! if (mode != SImode && mode != word_mode)
FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
--- 2309,2315 ----
count = INTVAL (operands[2]);
regno = REGNO (operands[0]);
mode = GET_MODE (operands[0]);
! if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
***************
*** 2342,2348 ****
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
(match_operand:DI 2 "s_operand" "QS"))])]
! "reload_completed && word_mode == DImode"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
--- 2347,2353 ----
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
(match_operand:DI 2 "s_operand" "QS"))])]
! "reload_completed && TARGET_ZARCH"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
***************
*** 2393,2399 ****
count = INTVAL (operands[2]);
regno = REGNO (operands[1]);
mode = GET_MODE (operands[1]);
! if (mode != SImode && mode != word_mode)
FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
--- 2398,2404 ----
count = INTVAL (operands[2]);
regno = REGNO (operands[1]);
mode = GET_MODE (operands[1]);
! if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
***************
*** 2433,2439 ****
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])]
! "reload_completed && word_mode == DImode"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
--- 2438,2444 ----
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])]
! "reload_completed && TARGET_ZARCH"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
***************
*** 2715,2725 ****
(clobber (reg:CC CC_REGNUM))])]
""
{
! enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
! rtx reg0 = gen_reg_rtx (dword_mode);
! rtx reg1 = gen_reg_rtx (dword_mode);
! rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
! rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1);
--- 2720,2731 ----
(clobber (reg:CC CC_REGNUM))])]
""
{
! enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
! enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
! rtx reg0 = gen_reg_rtx (dreg_mode);
! rtx reg1 = gen_reg_rtx (dreg_mode);
! rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
! rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1);
***************
*** 2745,2751 ****
(use (match_dup 2))
(use (match_dup 3))
(clobber (reg:CC CC_REGNUM))]
! ""
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
--- 2751,2770 ----
(use (match_dup 2))
(use (match_dup 3))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT || !TARGET_ZARCH"
! "mvcle\t%0,%1,0\;jo\t.-4"
! [(set_attr "length" "8")
! (set_attr "type" "vs")])
!
! (define_insn "*movmem_long_31z"
! [(clobber (match_operand:TI 0 "register_operand" "=d"))
! (clobber (match_operand:TI 1 "register_operand" "=d"))
! (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
! (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
! (use (match_dup 2))
! (use (match_dup 3))
! (clobber (reg:CC CC_REGNUM))]
! "!TARGET_64BIT && TARGET_ZARCH"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
***************
*** 2917,2926 ****
(clobber (reg:CC CC_REGNUM))])]
""
{
! enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
! rtx reg0 = gen_reg_rtx (dword_mode);
! rtx reg1 = gen_reg_rtx (dword_mode);
! rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
rtx len0 = gen_lowpart (Pmode, reg0);
emit_clobber (reg0);
--- 2936,2946 ----
(clobber (reg:CC CC_REGNUM))])]
""
{
! enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
! enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
! rtx reg0 = gen_reg_rtx (dreg_mode);
! rtx reg1 = gen_reg_rtx (dreg_mode);
! rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
rtx len0 = gen_lowpart (Pmode, reg0);
emit_clobber (reg0);
***************
*** 2941,2947 ****
(use (match_dup 3))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
! ""
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
--- 2961,2967 ----
(use (match_dup 3))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT || !TARGET_ZARCH"
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
***************
*** 2954,2963 ****
(use (match_dup 3))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
! "(INTVAL (operands[4]) & 255) == 255"
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
;
; cmpmemM instruction pattern(s).
;
--- 2974,2997 ----
(use (match_dup 3))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
! "(TARGET_64BIT || !TARGET_ZARCH) &&
! (INTVAL (operands[4]) & 255) == 255"
! "mvcle\t%0,%1,%Y2\;jo\t.-4"
! [(set_attr "length" "8")
! (set_attr "type" "vs")])
!
! (define_insn "*setmem_long_31z"
! [(clobber (match_operand:TI 0 "register_operand" "=d"))
! (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
! (match_operand 2 "shift_count_or_setmem_operand" "Y"))
! (use (match_dup 3))
! (use (match_operand:TI 1 "register_operand" "d"))
! (clobber (reg:CC CC_REGNUM))]
! "!TARGET_64BIT && TARGET_ZARCH"
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
+
;
; cmpmemM instruction pattern(s).
;
***************
*** 3071,3081 ****
(use (match_dup 3))])]
""
{
! enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
! rtx reg0 = gen_reg_rtx (dword_mode);
! rtx reg1 = gen_reg_rtx (dword_mode);
! rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
! rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1);
--- 3105,3116 ----
(use (match_dup 3))])]
""
{
! enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
! enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
! rtx reg0 = gen_reg_rtx (dreg_mode);
! rtx reg1 = gen_reg_rtx (dreg_mode);
! rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
! rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1);
***************
*** 3101,3111 ****
(mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
(use (match_dup 2))
(use (match_dup 3))]
! ""
"clcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
; Convert CCUmode condition code to integer.
; Result is zero if EQ, positive if LTU, negative if GTU.
--- 3136,3160 ----
(mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
(use (match_dup 2))
(use (match_dup 3))]
! "TARGET_64BIT || !TARGET_ZARCH"
"clcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
+ (define_insn "*cmpmem_long_31z"
+ [(clobber (match_operand:TI 0 "register_operand" "=d"))
+ (clobber (match_operand:TI 1 "register_operand" "=d"))
+ (set (reg:CCU CC_REGNUM)
+ (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
+ (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
+ (use (match_dup 2))
+ (use (match_dup 3))]
+ "!TARGET_64BIT && TARGET_ZARCH"
+ "clcle\t%0,%1,0\;jo\t.-4"
+ [(set_attr "op_type" "NN")
+ (set_attr "type" "vs")
+ (set_attr "length" "8")])
+
; Convert CCUmode condition code to integer.
; Result is zero if EQ, positive if LTU, negative if GTU.
***************
*** 3147,3153 ****
(sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
UNSPEC_CCU_TO_INT)))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
--- 3196,3202 ----
(sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
UNSPEC_CCU_TO_INT)))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
***************
*** 3164,3170 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
! "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
--- 3213,3219 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
! "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
***************
*** 3199,3205 ****
(unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
(match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"icmh\t%0,%2,%S1"
[(set_attr "op_type" "RSY")
(set_attr "z10prop" "z10_super")])
--- 3248,3254 ----
(unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
(match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"icmh\t%0,%2,%S1"
[(set_attr "op_type" "RSY")
(set_attr "z10prop" "z10_super")])
***************
*** 3209,3215 ****
(unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
(match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_64BIT"
"@
icm\t%0,%2,%S1
icmy\t%0,%2,%S1"
--- 3258,3264 ----
(unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
(match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_ZARCH"
"@
icm\t%0,%2,%S1
icmy\t%0,%2,%S1"
***************
*** 3365,3374 ****
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
! [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
(match_operand 1 "const_int_operand" "n,n")
(const_int 0))
! (match_operand:P 2 "register_operand" "d,d"))]
"INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
--- 3414,3423 ----
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
! [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
(match_operand 1 "const_int_operand" "n,n")
(const_int 0))
! (match_operand:W 2 "register_operand" "d,d"))]
"INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
***************
*** 3388,3394 ****
(const_int 0))
(lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
(const_int 32)))]
! "TARGET_64BIT
&& INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
--- 3437,3443 ----
(const_int 0))
(lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
(const_int 32)))]
! "TARGET_ZARCH
&& INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
***************
*** 3401,3411 ****
[(set_attr "op_type" "RSY")
(set_attr "z10prop" "z10_super")])
! (define_insn "*insv<mode>_reg_imm"
! [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
! (const_int 16)
! (match_operand 1 "const_int_operand" "n"))
! (match_operand:P 2 "const_int_operand" "n"))]
"TARGET_ZARCH
&& INTVAL (operands[1]) >= 0
&& INTVAL (operands[1]) < BITS_PER_WORD
--- 3450,3460 ----
[(set_attr "op_type" "RSY")
(set_attr "z10prop" "z10_super")])
! (define_insn "*insvdi_reg_imm"
! [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
! (const_int 16)
! (match_operand 1 "const_int_operand" "n"))
! (match_operand:DI 2 "const_int_operand" "n"))]
"TARGET_ZARCH
&& INTVAL (operands[1]) >= 0
&& INTVAL (operands[1]) < BITS_PER_WORD
***************
*** 3455,3461 ****
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
{
! if (!TARGET_64BIT)
{
emit_clobber (operands[0]);
emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
--- 3504,3510 ----
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
{
! if (!TARGET_ZARCH)
{
emit_clobber (operands[0]);
emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
***************
*** 3468,3474 ****
(define_insn "*extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
! "TARGET_64BIT"
"@
lgfr\t%0,%1
lgf\t%0,%1
--- 3517,3523 ----
(define_insn "*extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
! "TARGET_ZARCH"
"@
lgfr\t%0,%1
lgf\t%0,%1
***************
*** 3487,3493 ****
(sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
{
! if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
--- 3536,3542 ----
(sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
{
! if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
***************
*** 3513,3519 ****
(define_insn "*extendhidi2_extimm"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
! "TARGET_64BIT && TARGET_EXTIMM"
"@
lghr\t%0,%1
lgh\t%0,%1
--- 3562,3568 ----
(define_insn "*extendhidi2_extimm"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
! "TARGET_ZARCH && TARGET_EXTIMM"
"@
lghr\t%0,%1
lgh\t%0,%1
***************
*** 3526,3532 ****
(define_insn "*extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
! "TARGET_64BIT"
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")
(set_attr "z10prop" "z10_super_E1")])
--- 3575,3581 ----
(define_insn "*extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
! "TARGET_ZARCH"
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")
(set_attr "z10prop" "z10_super_E1")])
***************
*** 3612,3618 ****
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
{
! if (!TARGET_64BIT)
{
emit_clobber (operands[0]);
emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
--- 3661,3667 ----
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
{
! if (!TARGET_ZARCH)
{
emit_clobber (operands[0]);
emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
***************
*** 3624,3630 ****
(define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
! "TARGET_64BIT"
"@
llgfr\t%0,%1
llgf\t%0,%1
--- 3673,3679 ----
(define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
! "TARGET_ZARCH"
"@
llgfr\t%0,%1
llgf\t%0,%1
***************
*** 3642,3648 ****
[(set (match_operand:DI 0 "register_operand" "=d")
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))]
! "TARGET_64BIT"
"llgt\t%0,%1"
[(set_attr "op_type" "RXE")
(set_attr "z10prop" "z10_super_E1")])
--- 3691,3697 ----
[(set (match_operand:DI 0 "register_operand" "=d")
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))]
! "TARGET_ZARCH"
"llgt\t%0,%1"
[(set_attr "op_type" "RXE")
(set_attr "z10prop" "z10_super_E1")])
***************
*** 3652,3658 ****
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0)
--- 3701,3707 ----
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0)
***************
*** 3675,3681 ****
[(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
(const_int 2147483647)))]
! "TARGET_64BIT"
"@
llgtr\t%0,%1
llgt\t%0,%N1"
--- 3724,3730 ----
[(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
(const_int 2147483647)))]
! "TARGET_ZARCH"
"@
llgtr\t%0,%1
llgt\t%0,%N1"
***************
*** 3683,3695 ****
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_split
! [(set (match_operand:GPR 0 "register_operand" "")
! (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && reload_completed"
[(set (match_dup 0)
! (and:GPR (match_dup 1)
(const_int 2147483647)))]
"")
--- 3732,3744 ----
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_split
! [(set (match_operand:DSI 0 "register_operand" "")
! (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && reload_completed"
[(set (match_dup 0)
! (and:DSI (match_dup 1)
(const_int 2147483647)))]
"")
***************
*** 3702,3708 ****
(zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
{
! if (!TARGET_64BIT)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
--- 3751,3757 ----
(zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
{
! if (!TARGET_ZARCH)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
***************
*** 3954,3960 ****
(define_expand "fix_trunc<mode>di2"
[(set (match_operand:DI 0 "register_operand" "")
(fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
! "TARGET_64BIT && TARGET_HARD_DFP"
{
operands[1] = force_reg (<MODE>mode, operands[1]);
emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
--- 4003,4009 ----
(define_expand "fix_trunc<mode>di2"
[(set (match_operand:DI 0 "register_operand" "")
(fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
! "TARGET_ZARCH && TARGET_HARD_DFP"
{
operands[1] = force_reg (<MODE>mode, operands[1]);
emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
***************
*** 3968,3974 ****
(fix:DI (match_operand:DFP 1 "register_operand" "f")))
(unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT && TARGET_HARD_DFP"
"cg<DFP:xde>tr\t%0,%h2,%1"
[(set_attr "op_type" "RRF")
(set_attr "type" "ftoidfp")])
--- 4017,4023 ----
(fix:DI (match_operand:DFP 1 "register_operand" "f")))
(unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH && TARGET_HARD_DFP"
"cg<DFP:xde>tr\t%0,%h2,%1"
[(set_attr "op_type" "RRF")
(set_attr "type" "ftoidfp")])
***************
*** 3995,4001 ****
(define_insn "floatdi<mode>2"
[(set (match_operand:FP 0 "register_operand" "=f")
(float:FP (match_operand:DI 1 "register_operand" "d")))]
! "TARGET_64BIT && TARGET_HARD_FLOAT"
"c<xde>g<bt>r\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof<mode>" )])
--- 4044,4050 ----
(define_insn "floatdi<mode>2"
[(set (match_operand:FP 0 "register_operand" "=f")
(float:FP (match_operand:DI 1 "register_operand" "d")))]
! "TARGET_ZARCH && TARGET_HARD_FLOAT"
"c<xde>g<bt>r\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof<mode>" )])
***************
*** 4237,4243 ****
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
(match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"#"
"&& reload_completed"
[(parallel
--- 4286,4292 ----
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
(match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
***************
*** 4275,4281 ****
(plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"@
agfr\t%0,%2
agf\t%0,%2"
--- 4324,4330 ----
(plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"@
agfr\t%0,%2
agf\t%0,%2"
***************
*** 4288,4294 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
! "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
algfr\t%0,%2
algf\t%0,%2"
--- 4337,4343 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
! "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
algfr\t%0,%2
algf\t%0,%2"
***************
*** 4301,4307 ****
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
! "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
algfr\t%0,%2
algf\t%0,%2"
--- 4350,4356 ----
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
! "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
algfr\t%0,%2
algf\t%0,%2"
***************
*** 4313,4319 ****
(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"@
algfr\t%0,%2
algf\t%0,%2"
--- 4362,4368 ----
(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"@
algfr\t%0,%2
algf\t%0,%2"
***************
*** 4325,4331 ****
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_64BIT && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
--- 4374,4380 ----
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
***************
*** 4645,4651 ****
(minus:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"#"
"&& reload_completed"
[(parallel
--- 4694,4700 ----
(minus:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
***************
*** 4682,4688 ****
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"@
sgfr\t%0,%2
sgf\t%0,%2"
--- 4731,4737 ----
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"@
sgfr\t%0,%2
sgf\t%0,%2"
***************
*** 4696,4702 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
! "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
slgfr\t%0,%2
slgf\t%0,%2"
--- 4745,4751 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
! "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
slgfr\t%0,%2
slgf\t%0,%2"
***************
*** 4709,4715 ****
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
! "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
slgfr\t%0,%2
slgf\t%0,%2"
--- 4758,4764 ----
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
! "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
slgfr\t%0,%2
slgf\t%0,%2"
***************
*** 4721,4727 ****
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"@
slgfr\t%0,%2
slgf\t%0,%2"
--- 4770,4776 ----
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"@
slgfr\t%0,%2
slgf\t%0,%2"
***************
*** 4733,4739 ****
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_64BIT && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
--- 4782,4788 ----
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
***************
*** 5197,5203 ****
[(set (match_operand:DI 0 "register_operand" "=d,d")
(mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))]
! "TARGET_64BIT"
"@
msgfr\t%0,%2
msgf\t%0,%2"
--- 5246,5252 ----
[(set (match_operand:DI 0 "register_operand" "=d,d")
(mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))]
! "TARGET_ZARCH"
"@
msgfr\t%0,%2
msgf\t%0,%2"
***************
*** 5208,5214 ****
[(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
! "TARGET_64BIT"
"@
msgr\t%0,%2
mghi\t%0,%h2
--- 5257,5263 ----
[(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
! "TARGET_ZARCH"
"@
msgr\t%0,%2
mghi\t%0,%h2
***************
*** 5259,5265 ****
(match_operand:SI 1 "register_operand" "%0,0,0"))
(sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
! "!TARGET_64BIT"
"@
mr\t%0,%2
m\t%0,%2
--- 5308,5314 ----
(match_operand:SI 1 "register_operand" "%0,0,0"))
(sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
! "!TARGET_ZARCH"
"@
mr\t%0,%2
m\t%0,%2
***************
*** 5278,5284 ****
(match_operand:SI 1 "register_operand" "%0,0"))
(zero_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
! "!TARGET_64BIT && TARGET_CPU_ZARCH"
"@
mlr\t%0,%2
ml\t%0,%2"
--- 5327,5333 ----
(match_operand:SI 1 "register_operand" "%0,0"))
(zero_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
! "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"@
mlr\t%0,%2
ml\t%0,%2"
***************
*** 5342,5348 ****
(set (match_operand:DI 3 "general_operand" "")
(mod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
! "TARGET_64BIT"
{
rtx insn, div_equal, mod_equal;
--- 5391,5397 ----
(set (match_operand:DI 3 "general_operand" "")
(mod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
! "TARGET_ZARCH"
{
rtx insn, div_equal, mod_equal;
***************
*** 5370,5376 ****
(match_operand:DI 2 "general_operand" "d,RT")))
(const_int 64))
(zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
! "TARGET_64BIT"
"@
dsgr\t%0,%2
dsg\t%0,%2"
--- 5419,5425 ----
(match_operand:DI 2 "general_operand" "d,RT")))
(const_int 64))
(zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
! "TARGET_ZARCH"
"@
dsgr\t%0,%2
dsg\t%0,%2"
***************
*** 5388,5394 ****
(const_int 64))
(zero_extend:TI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
! "TARGET_64BIT"
"@
dsgfr\t%0,%2
dsgf\t%0,%2"
--- 5437,5443 ----
(const_int 64))
(zero_extend:TI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
! "TARGET_ZARCH"
"@
dsgfr\t%0,%2
dsgf\t%0,%2"
***************
*** 5406,5412 ****
(set (match_operand:DI 3 "general_operand" "")
(umod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
! "TARGET_64BIT"
{
rtx insn, div_equal, mod_equal, equal;
--- 5455,5461 ----
(set (match_operand:DI 3 "general_operand" "")
(umod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
! "TARGET_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
***************
*** 5448,5454 ****
(zero_extend:TI
(truncate:DI
(udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
! "TARGET_64BIT"
"@
dlgr\t%0,%2
dlg\t%0,%2"
--- 5497,5503 ----
(zero_extend:TI
(truncate:DI
(udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
! "TARGET_ZARCH"
"@
dlgr\t%0,%2
dlg\t%0,%2"
***************
*** 5466,5472 ****
(set (match_operand:SI 3 "general_operand" "")
(mod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
! "!TARGET_64BIT"
{
rtx insn, div_equal, mod_equal, equal;
--- 5515,5521 ----
(set (match_operand:SI 3 "general_operand" "")
(mod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
! "!TARGET_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
***************
*** 5506,5512 ****
(zero_extend:DI
(truncate:SI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
! "!TARGET_64BIT"
"@
dr\t%0,%2
d\t%0,%2"
--- 5555,5561 ----
(zero_extend:DI
(truncate:SI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
! "!TARGET_ZARCH"
"@
dr\t%0,%2
d\t%0,%2"
***************
*** 5524,5530 ****
(set (match_operand:SI 3 "general_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
! "!TARGET_64BIT && TARGET_CPU_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
--- 5573,5579 ----
(set (match_operand:SI 3 "general_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
! "!TARGET_ZARCH && TARGET_CPU_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
***************
*** 5566,5572 ****
(zero_extend:DI
(truncate:SI
(udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
! "!TARGET_64BIT && TARGET_CPU_ZARCH"
"@
dlr\t%0,%2
dl\t%0,%2"
--- 5615,5621 ----
(zero_extend:DI
(truncate:SI
(udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
! "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"@
dlr\t%0,%2
dl\t%0,%2"
***************
*** 5578,5584 ****
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))
(clobber (match_dup 3))]
! "!TARGET_64BIT && !TARGET_CPU_ZARCH"
{
rtx insn, udiv_equal, umod_equal, equal;
--- 5627,5633 ----
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))
(clobber (match_dup 3))]
! "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
{
rtx insn, udiv_equal, umod_equal, equal;
***************
*** 5664,5670 ****
(umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "nonimmediate_operand" "")))
(clobber (match_dup 3))]
! "!TARGET_64BIT && !TARGET_CPU_ZARCH"
{
rtx insn, udiv_equal, umod_equal, equal;
--- 5713,5719 ----
(umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "nonimmediate_operand" "")))
(clobber (match_dup 3))]
! "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
{
rtx insn, udiv_equal, umod_equal, equal;
***************
*** 5785,5791 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
ngr\t%0,%2
ng\t%0,%2"
--- 5834,5840 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ngr\t%0,%2
ng\t%0,%2"
***************
*** 5798,5804 ****
(match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@
--- 5847,5853 ----
(match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@
***************
*** 5814,5820 ****
(match_operand:DI 2 "general_operand"
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
#
#
--- 5863,5869 ----
(match_operand:DI 2 "general_operand"
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
#
#
***************
*** 6104,6110 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(ior:DI (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
ogr\t%0,%2
og\t%0,%2"
--- 6153,6159 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(ior:DI (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ogr\t%0,%2
og\t%0,%2"
***************
*** 6117,6123 ****
(match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
ogr\t%0,%2
og\t%0,%2"
--- 6166,6172 ----
(match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ogr\t%0,%2
og\t%0,%2"
***************
*** 6130,6136 ****
(match_operand:DI 2 "general_operand"
"N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
oihh\t%0,%i2
oihl\t%0,%i2
--- 6179,6185 ----
(match_operand:DI 2 "general_operand"
"N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
oihh\t%0,%i2
oihl\t%0,%i2
***************
*** 6404,6410 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(xor:DI (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
xgr\t%0,%2
xg\t%0,%2"
--- 6453,6459 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(xor:DI (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
xgr\t%0,%2
xg\t%0,%2"
***************
*** 6417,6423 ****
(match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
xgr\t%0,%2
xg\t%0,%2"
--- 6466,6472 ----
(match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
xgr\t%0,%2
xg\t%0,%2"
***************
*** 6429,6435 ****
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
(match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
"@
xihf\t%0,%k2
xilf\t%0,%k2
--- 6478,6484 ----
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
(match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
xihf\t%0,%k2
xilf\t%0,%k2
***************
*** 6676,6682 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_dup 1))))]
! "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
--- 6725,6731 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_dup 1))))]
! "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
***************
*** 6685,6691 ****
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
--- 6734,6740 ----
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
***************
*** 6727,6733 ****
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_64BIT"
"#"
"&& reload_completed"
[(parallel
--- 6776,6782 ----
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
***************
*** 6822,6828 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_dup 1))))]
! "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
--- 6871,6877 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_dup 1))))]
! "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
***************
*** 6831,6837 ****
[(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
--- 6880,6886 ----
[(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
***************
*** 6940,6946 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
! "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
--- 6989,6995 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
! "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
***************
*** 6950,6956 ****
(neg:DI (abs:DI (sign_extend:DI
(match_operand:SI 1 "register_operand" "d")))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
--- 6999,7005 ----
(neg:DI (abs:DI (sign_extend:DI
(match_operand:SI 1 "register_operand" "d")))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
***************
*** 7079,7085 ****
(define_expand "clzdi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(clz:DI (match_operand:DI 1 "register_operand" "d")))]
! "TARGET_EXTIMM && TARGET_64BIT"
{
rtx insn, clz_equal;
rtx wide_reg = gen_reg_rtx (TImode);
--- 7128,7134 ----
(define_expand "clzdi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(clz:DI (match_operand:DI 1 "register_operand" "d")))]
! "TARGET_EXTIMM && TARGET_ZARCH"
{
rtx insn, clz_equal;
rtx wide_reg = gen_reg_rtx (TImode);
***************
*** 7109,7115 ****
(clobber (reg:CC CC_REGNUM))]
"(unsigned HOST_WIDE_INT) INTVAL (operands[2])
== (unsigned HOST_WIDE_INT) 1 << 63
! && TARGET_EXTIMM && TARGET_64BIT"
"flogr\t%0,%1"
[(set_attr "op_type" "RRE")])
--- 7158,7164 ----
(clobber (reg:CC CC_REGNUM))]
"(unsigned HOST_WIDE_INT) INTVAL (operands[2])
== (unsigned HOST_WIDE_INT) 1 << 63
! && TARGET_EXTIMM && TARGET_ZARCH"
"flogr\t%0,%1"
[(set_attr "op_type" "RRE")])
***************
*** 7166,7172 ****
[(set (match_operand:DI 0 "register_operand" "=d")
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
! "!TARGET_64BIT"
"s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 7215,7221 ----
[(set (match_operand:DI 0 "register_operand" "=d")
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
! "!TARGET_ZARCH"
"s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
***************
*** 7188,7194 ****
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n"))))]
! "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
"s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 7237,7243 ----
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n"))))]
! "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
"s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
***************
*** 7225,7231 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
! "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 7274,7280 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
! "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
***************
*** 7236,7242 ****
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
! "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 7285,7291 ----
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
! "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
***************
*** 7246,7252 ****
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_64BIT"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 7295,7301 ----
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_ZARCH"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
***************
*** 7301,7307 ****
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
! "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
&& (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
--- 7350,7356 ----
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
! "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
&& (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
***************
*** 7314,7320 ****
(match_operand:SI 3 "const_int_operand" "n")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
! "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
&& (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
--- 7363,7369 ----
(match_operand:SI 3 "const_int_operand" "n")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
! "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
&& (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
***************
*** 7326,7332 ****
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n"))))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 7375,7381 ----
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n"))))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
***************
*** 7680,7686 ****
(subreg:DI (match_dup 2) 0)))
(clobber (match_scratch:DI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
{
if (which_alternative != 0)
return "#";
--- 7729,7735 ----
(subreg:DI (match_dup 2) 0)))
(clobber (match_scratch:DI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
{
if (which_alternative != 0)
return "#";
***************
*** 7723,7729 ****
(subreg:SI (match_dup 2) 4)))
(clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
{
if (which_alternative != 0)
return "#";
--- 7772,7778 ----
(subreg:SI (match_dup 2) 4)))
(clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
{
if (which_alternative != 0)
return "#";
***************
*** 7766,7772 ****
(subreg:SI (match_dup 2) 0)))
(clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_64BIT && TARGET_CPU_ZARCH"
{
if (which_alternative != 0)
return "#";
--- 7815,7821 ----
(subreg:SI (match_dup 2) 0)))
(clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_ZARCH && TARGET_CPU_ZARCH"
{
if (which_alternative != 0)
return "#";
***************
*** 7808,7814 ****
emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
! else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
else
FAIL;
--- 7857,7863 ----
emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
! else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
else
FAIL;
***************
*** 7939,7945 ****
(plus:DI (match_dup 1) (const_int -1)))
(clobber (match_scratch:DI 3 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_64BIT"
{
if (which_alternative != 0)
return "#";
--- 7988,7994 ----
(plus:DI (match_dup 1) (const_int -1)))
(clobber (match_scratch:DI 3 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_ZARCH"
{
if (which_alternative != 0)
return "#";
***************
*** 8497,8509 ****
; cds, cdsg
(define_insn "*sync_compare_and_swap<mode>"
! [(set (match_operand:DP 0 "register_operand" "=r")
! (match_operand:DP 1 "memory_operand" "+Q"))
(set (match_dup 1)
! (unspec_volatile:DP
[(match_dup 1)
! (match_operand:DP 2 "register_operand" "0")
! (match_operand:DP 3 "register_operand" "r")]
UNSPECV_CAS))
(set (reg:CCZ1 CC_REGNUM)
(compare:CCZ1 (match_dup 1) (match_dup 2)))]
--- 8546,8558 ----
; cds, cdsg
(define_insn "*sync_compare_and_swap<mode>"
! [(set (match_operand:DW 0 "register_operand" "=r")
! (match_operand:DW 1 "memory_operand" "+Q"))
(set (match_dup 1)
! (unspec_volatile:DW
[(match_dup 1)
! (match_operand:DW 2 "register_operand" "0")
! (match_operand:DW 3 "register_operand" "r")]
UNSPECV_CAS))
(set (reg:CCZ1 CC_REGNUM)
(compare:CCZ1 (match_dup 1) (match_dup 2)))]
***************
*** 8646,8665 ****
(match_operand 1 "register_operand" "")]
""
{
- enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
/* Copy the backchain to the first word, sp to the second and the
literal pool base to the third. */
if (TARGET_BACKCHAIN)
! {
! rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
! emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
! }
! emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
! emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
DONE;
})
--- 8695,8714 ----
(match_operand 1 "register_operand" "")]
""
{
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
/* Copy the backchain to the first word, sp to the second and the
literal pool base to the third. */
+ rtx save_bc = adjust_address (operands[0], Pmode, 0);
+ rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
+ rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
+
if (TARGET_BACKCHAIN)
! emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
! emit_move_insn (save_sp, operands[1]);
! emit_move_insn (save_bp, base);
DONE;
})
***************
*** 8669,8686 ****
(match_operand 1 "memory_operand" "")]
""
{
- enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
rtx temp = NULL_RTX;
/* Restore the backchain from the first word, sp from the second and the
literal pool base from the third. */
if (TARGET_BACKCHAIN)
! temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
! emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
! emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
if (temp)
emit_move_insn (s390_back_chain_rtx (), temp);
--- 8718,8738 ----
(match_operand 1 "memory_operand" "")]
""
{
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
rtx temp = NULL_RTX;
/* Restore the backchain from the first word, sp from the second and the
literal pool base from the third. */
+ rtx save_bc = adjust_address (operands[1], Pmode, 0);
+ rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
+ rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
+
if (TARGET_BACKCHAIN)
! temp = force_reg (Pmode, save_bc);
! emit_move_insn (base, save_bp);
! emit_move_insn (operands[0], save_sp);
if (temp)
emit_move_insn (s390_back_chain_rtx (), temp);
Index: gcc/config/s390/s390.c
===================================================================
*** gcc/config/s390/s390.c.orig
--- gcc/config/s390/s390.c
*************** struct GTY(()) machine_function
*** 324,330 ****
#define cfun_frame_layout (cfun->machine->frame_layout)
#define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
! cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
#define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
(1 << (BITNUM)))
#define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
--- 324,330 ----
#define cfun_frame_layout (cfun->machine->frame_layout)
#define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
! cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
#define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
(1 << (BITNUM)))
#define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
*************** s390_libgcc_shift_count_mode (void)
*** 365,378 ****
return TARGET_64BIT ? DImode : SImode;
}
/* Return true if the back end supports mode MODE. */
static bool
s390_scalar_mode_supported_p (enum machine_mode mode)
{
if (DECIMAL_FLOAT_MODE_P (mode))
return default_decimal_float_supported_p ();
! else
! return default_scalar_mode_supported_p (mode);
}
/* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
--- 365,389 ----
return TARGET_64BIT ? DImode : SImode;
}
+ static enum machine_mode
+ s390_unwind_word_mode (void)
+ {
+ return TARGET_64BIT ? DImode : SImode;
+ }
+
/* Return true if the back end supports mode MODE. */
static bool
s390_scalar_mode_supported_p (enum machine_mode mode)
{
+ /* In contrast to the default implementation reject TImode constants on 31bit
+ TARGET_ZARCH for ABI compliance. */
+ if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
+ return false;
+
if (DECIMAL_FLOAT_MODE_P (mode))
return default_decimal_float_supported_p ();
!
! return default_scalar_mode_supported_p (mode);
}
/* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
*************** s390_rtx_costs (rtx x, int code, int out
*** 2407,2413 ****
{
rtx left = XEXP (x, 0);
rtx right = XEXP (x, 1);
! if (TARGET_64BIT)
{
if (GET_CODE (right) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (right)))
--- 2418,2424 ----
{
rtx left = XEXP (x, 0);
rtx right = XEXP (x, 1);
! if (TARGET_ZARCH)
{
if (GET_CODE (right) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (right)))
*************** s390_rtx_costs (rtx x, int code, int out
*** 2468,2474 ****
{
rtx right = XEXP (x, 1);
if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
! if (TARGET_64BIT)
*total = s390_cost->dsgfr;
else
*total = s390_cost->dr;
--- 2479,2485 ----
{
rtx right = XEXP (x, 1);
if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
! if (TARGET_ZARCH)
*total = s390_cost->dsgfr;
else
*total = s390_cost->dr;
*************** s390_secondary_reload (bool in_p, rtx x,
*** 2960,2966 ****
if (MEM_P (x)
&& s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
&& (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
! || (!TARGET_64BIT && mode == DImode)
|| ((mode == HImode || mode == SImode || mode == DImode)
&& (!s390_check_symref_alignment (XEXP (x, 0),
GET_MODE_SIZE (mode))))))
--- 2971,2977 ----
if (MEM_P (x)
&& s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
&& (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
! || (!TARGET_ZARCH && mode == DImode)
|| ((mode == HImode || mode == SImode || mode == DImode)
&& (!s390_check_symref_alignment (XEXP (x, 0),
GET_MODE_SIZE (mode))))))
*************** s390_expand_setmem (rtx dst, rtx len, rt
*** 4033,4039 ****
else
{
! rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
rtx loop_start_label = gen_label_rtx ();
rtx loop_end_label = gen_label_rtx ();
rtx end_label = gen_label_rtx ();
--- 4044,4050 ----
else
{
! rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
rtx loop_start_label = gen_label_rtx ();
rtx loop_end_label = gen_label_rtx ();
rtx end_label = gen_label_rtx ();
*************** s390_expand_setmem (rtx dst, rtx len, rt
*** 4044,4050 ****
mode = Pmode;
dst_addr = gen_reg_rtx (Pmode);
- src_addr = gen_reg_rtx (Pmode);
count = gen_reg_rtx (mode);
blocks = gen_reg_rtx (mode);
--- 4055,4060 ----
*************** s390_first_cycle_multipass_dfa_lookahead
*** 5412,5418 ****
return 4;
}
-
/* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
Fix up MEMs as required. */
--- 5422,5427 ----
*************** s390_return_addr_rtx (int count, rtx fra
*** 6810,6818 ****
}
if (TARGET_PACKED_STACK)
! offset = -2 * UNITS_PER_WORD;
else
! offset = RETURN_REGNUM * UNITS_PER_WORD;
addr = plus_constant (frame, offset);
addr = memory_address (Pmode, addr);
--- 6819,6827 ----
}
if (TARGET_PACKED_STACK)
! offset = -2 * UNITS_PER_LONG;
else
! offset = RETURN_REGNUM * UNITS_PER_LONG;
addr = plus_constant (frame, offset);
addr = memory_address (Pmode, addr);
*************** s390_back_chain_rtx (void)
*** 6831,6837 ****
if (TARGET_PACKED_STACK)
chain = plus_constant (stack_pointer_rtx,
! STACK_POINTER_OFFSET - UNITS_PER_WORD);
else
chain = stack_pointer_rtx;
--- 6840,6846 ----
if (TARGET_PACKED_STACK)
chain = plus_constant (stack_pointer_rtx,
! STACK_POINTER_OFFSET - UNITS_PER_LONG);
else
chain = stack_pointer_rtx;
*************** s390_frame_area (int *area_bottom, int *
*** 6956,6964 ****
if (cfun_frame_layout.first_restore_gpr != -1)
{
b = (cfun_frame_layout.gprs_offset
! + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
t = b + (cfun_frame_layout.last_restore_gpr
! - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
}
if (TARGET_64BIT && cfun_save_high_fprs_p)
--- 6965,6973 ----
if (cfun_frame_layout.first_restore_gpr != -1)
{
b = (cfun_frame_layout.gprs_offset
! + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
t = b + (cfun_frame_layout.last_restore_gpr
! - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
}
if (TARGET_64BIT && cfun_save_high_fprs_p)
*************** s390_frame_info (void)
*** 7153,7172 ****
if (!TARGET_PACKED_STACK)
{
cfun_frame_layout.backchain_offset = 0;
! cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
! * UNITS_PER_WORD);
}
else if (TARGET_BACKCHAIN) /* kernel stack layout */
{
cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
! - UNITS_PER_WORD);
cfun_frame_layout.gprs_offset
= (cfun_frame_layout.backchain_offset
- (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
! * UNITS_PER_WORD);
if (TARGET_64BIT)
{
--- 7162,7181 ----
if (!TARGET_PACKED_STACK)
{
cfun_frame_layout.backchain_offset = 0;
! cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
! * UNITS_PER_LONG);
}
else if (TARGET_BACKCHAIN) /* kernel stack layout */
{
cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
! - UNITS_PER_LONG);
cfun_frame_layout.gprs_offset
= (cfun_frame_layout.backchain_offset
- (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
! * UNITS_PER_LONG);
if (TARGET_64BIT)
{
*************** s390_frame_info (void)
*** 7221,7227 ****
else
{
if (TARGET_BACKCHAIN)
! cfun_frame_layout.frame_size += UNITS_PER_WORD;
/* No alignment trouble here because f8-f15 are only saved under
64 bit. */
--- 7230,7236 ----
else
{
if (TARGET_BACKCHAIN)
! cfun_frame_layout.frame_size += UNITS_PER_LONG;
/* No alignment trouble here because f8-f15 are only saved under
64 bit. */
*************** s390_hard_regno_mode_ok (unsigned int re
*** 7340,7346 ****
case GENERAL_REGS:
if (REGNO_PAIR_OK (regno, mode))
{
! if (TARGET_64BIT
|| (mode != TFmode && mode != TCmode && mode != TDmode))
return true;
}
--- 7349,7355 ----
case GENERAL_REGS:
if (REGNO_PAIR_OK (regno, mode))
{
! if (TARGET_ZARCH
|| (mode != TFmode && mode != TCmode && mode != TDmode))
return true;
}
*************** s390_initial_elimination_offset (int fro
*** 7471,7477 ****
index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
gcc_assert (index >= 0);
offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
! offset += index * UNITS_PER_WORD;
break;
case BASE_REGNUM:
--- 7480,7486 ----
index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
gcc_assert (index >= 0);
offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
! offset += index * UNITS_PER_LONG;
break;
case BASE_REGNUM:
*************** save_gprs (rtx base, int offset, int fir
*** 7607,7613 ****
if (start > last)
return insn;
! addr = plus_constant (base, offset + (start - first) * UNITS_PER_WORD);
note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
gen_rtx_REG (Pmode, start),
GEN_INT (last - start + 1));
--- 7616,7622 ----
if (start > last)
return insn;
! addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
gen_rtx_REG (Pmode, start),
GEN_INT (last - start + 1));
*************** s390_emit_prologue (void)
*** 7756,7762 ****
{
insn = save_gprs (stack_pointer_rtx,
cfun_frame_layout.gprs_offset +
! UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
- cfun_frame_layout.first_save_gpr_slot),
cfun_frame_layout.first_save_gpr,
cfun_frame_layout.last_save_gpr);
--- 7765,7771 ----
{
insn = save_gprs (stack_pointer_rtx,
cfun_frame_layout.gprs_offset +
! UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
- cfun_frame_layout.first_save_gpr_slot),
cfun_frame_layout.first_save_gpr,
cfun_frame_layout.last_save_gpr);
*************** s390_emit_epilogue (bool sibcall)
*** 8153,8159 ****
addr = plus_constant (frame_pointer,
offset + cfun_frame_layout.gprs_offset
+ (i - cfun_frame_layout.first_save_gpr_slot)
! * UNITS_PER_WORD);
addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, get_frame_alias_set ());
emit_move_insn (addr, gen_rtx_REG (Pmode, i));
--- 8162,8168 ----
addr = plus_constant (frame_pointer,
offset + cfun_frame_layout.gprs_offset
+ (i - cfun_frame_layout.first_save_gpr_slot)
! * UNITS_PER_LONG);
addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, get_frame_alias_set ());
emit_move_insn (addr, gen_rtx_REG (Pmode, i));
*************** s390_emit_epilogue (bool sibcall)
*** 8182,8188 ****
offset + cfun_frame_layout.gprs_offset
+ (RETURN_REGNUM
- cfun_frame_layout.first_save_gpr_slot)
! * UNITS_PER_WORD);
addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, get_frame_alias_set ());
emit_move_insn (return_reg, addr);
--- 8191,8197 ----
offset + cfun_frame_layout.gprs_offset
+ (RETURN_REGNUM
- cfun_frame_layout.first_save_gpr_slot)
! * UNITS_PER_LONG);
addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, get_frame_alias_set ());
emit_move_insn (return_reg, addr);
*************** s390_emit_epilogue (bool sibcall)
*** 8193,8199 ****
offset + cfun_frame_layout.gprs_offset
+ (cfun_frame_layout.first_restore_gpr
- cfun_frame_layout.first_save_gpr_slot)
! * UNITS_PER_WORD,
cfun_frame_layout.first_restore_gpr,
cfun_frame_layout.last_restore_gpr);
insn = emit_insn (insn);
--- 8202,8208 ----
offset + cfun_frame_layout.gprs_offset
+ (cfun_frame_layout.first_restore_gpr
- cfun_frame_layout.first_save_gpr_slot)
! * UNITS_PER_LONG,
cfun_frame_layout.first_restore_gpr,
cfun_frame_layout.last_restore_gpr);
insn = emit_insn (insn);
*************** s390_function_arg_advance (CUMULATIVE_AR
*** 8357,8363 ****
else if (s390_function_arg_integer (mode, type))
{
int size = s390_function_arg_size (mode, type);
! cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
}
else
gcc_unreachable ();
--- 8366,8372 ----
else if (s390_function_arg_integer (mode, type))
{
int size = s390_function_arg_size (mode, type);
! cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
}
else
gcc_unreachable ();
*************** s390_function_arg (CUMULATIVE_ARGS *cum,
*** 8396,8407 ****
else if (s390_function_arg_integer (mode, type))
{
int size = s390_function_arg_size (mode, type);
! int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
return 0;
! else
return gen_rtx_REG (mode, cum->gprs + 2);
}
/* After the real arguments, expand_call calls us once again
--- 8405,8429 ----
else if (s390_function_arg_integer (mode, type))
{
int size = s390_function_arg_size (mode, type);
! int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
return 0;
! else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
return gen_rtx_REG (mode, cum->gprs + 2);
+ else if (n_gprs == 2)
+ {
+ rtvec p = rtvec_alloc (2);
+
+ RTVEC_ELT (p, 0)
+ = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
+ const0_rtx);
+ RTVEC_ELT (p, 1)
+ = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
+ GEN_INT (4));
+
+ return gen_rtx_PARALLEL (mode, p);
+ }
}
/* After the real arguments, expand_call calls us once again
*************** s390_promote_function_mode (const_tree t
*** 8451,8457 ****
int for_return ATTRIBUTE_UNUSED)
{
if (INTEGRAL_MODE_P (mode)
! && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
{
if (POINTER_TYPE_P (type))
*punsignedp = POINTERS_EXTEND_UNSIGNED;
--- 8473,8479 ----
int for_return ATTRIBUTE_UNUSED)
{
if (INTEGRAL_MODE_P (mode)
! && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
{
if (POINTER_TYPE_P (type))
*punsignedp = POINTERS_EXTEND_UNSIGNED;
*************** s390_function_value (const_tree type, co
*** 8479,8486 ****
if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
return gen_rtx_REG (mode, 16);
! else
return gen_rtx_REG (mode, 2);
}
--- 8501,8522 ----
if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
return gen_rtx_REG (mode, 16);
! else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
! || UNITS_PER_LONG == UNITS_PER_WORD)
return gen_rtx_REG (mode, 2);
+ else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
+ {
+ rtvec p = rtvec_alloc (2);
+
+ RTVEC_ELT (p, 0)
+ = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
+ RTVEC_ELT (p, 1)
+ = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
+
+ return gen_rtx_PARALLEL (mode, p);
+ }
+
+ gcc_unreachable ();
}
*************** s390_va_start (tree valist, rtx nextarg
*** 8628,8634 ****
{
t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
! size_int (-RETURN_REGNUM * UNITS_PER_WORD));
t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
TREE_SIDE_EFFECTS (t) = 1;
--- 8664,8670 ----
{
t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
! size_int (-RETURN_REGNUM * UNITS_PER_LONG));
t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
TREE_SIDE_EFFECTS (t) = 1;
*************** s390_gimplify_va_arg (tree valist, tree
*** 8702,8710 ****
/* kernel stack layout on 31 bit: It is assumed here that no padding
will be added by s390_frame_info because for va_args always an even
number of gprs has to be saved r15-r2 = 14 regs. */
! sav_ofs = 2 * UNITS_PER_WORD;
! sav_scale = UNITS_PER_WORD;
! size = UNITS_PER_WORD;
max_reg = GP_ARG_NUM_REG - n_reg;
}
else if (s390_function_arg_float (TYPE_MODE (type), type))
--- 8738,8746 ----
/* kernel stack layout on 31 bit: It is assumed here that no padding
will be added by s390_frame_info because for va_args always an even
number of gprs has to be saved r15-r2 = 14 regs. */
! sav_ofs = 2 * UNITS_PER_LONG;
! sav_scale = UNITS_PER_LONG;
! size = UNITS_PER_LONG;
max_reg = GP_ARG_NUM_REG - n_reg;
}
else if (s390_function_arg_float (TYPE_MODE (type), type))
*************** s390_gimplify_va_arg (tree valist, tree
*** 8719,8725 ****
indirect_p = 0;
reg = fpr;
n_reg = 1;
! sav_ofs = 16 * UNITS_PER_WORD;
sav_scale = 8;
max_reg = FP_ARG_NUM_REG - n_reg;
}
--- 8755,8761 ----
indirect_p = 0;
reg = fpr;
n_reg = 1;
! sav_ofs = 16 * UNITS_PER_LONG;
sav_scale = 8;
max_reg = FP_ARG_NUM_REG - n_reg;
}
*************** s390_gimplify_va_arg (tree valist, tree
*** 8734,8750 ****
/* Otherwise into GP registers. */
indirect_p = 0;
reg = gpr;
! n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
/* kernel stack layout on 31 bit: It is assumed here that no padding
will be added by s390_frame_info because for va_args always an even
number of gprs has to be saved r15-r2 = 14 regs. */
! sav_ofs = 2 * UNITS_PER_WORD;
! if (size < UNITS_PER_WORD)
! sav_ofs += UNITS_PER_WORD - size;
! sav_scale = UNITS_PER_WORD;
max_reg = GP_ARG_NUM_REG - n_reg;
}
--- 8770,8786 ----
/* Otherwise into GP registers. */
indirect_p = 0;
reg = gpr;
! n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
/* kernel stack layout on 31 bit: It is assumed here that no padding
will be added by s390_frame_info because for va_args always an even
number of gprs has to be saved r15-r2 = 14 regs. */
! sav_ofs = 2 * UNITS_PER_LONG;
! if (size < UNITS_PER_LONG)
! sav_ofs += UNITS_PER_LONG - size;
! sav_scale = UNITS_PER_LONG;
max_reg = GP_ARG_NUM_REG - n_reg;
}
*************** s390_gimplify_va_arg (tree valist, tree
*** 8776,8784 ****
/* ... Otherwise out of the overflow area. */
t = ovf;
! if (size < UNITS_PER_WORD)
t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
! size_int (UNITS_PER_WORD - size));
gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
--- 8812,8820 ----
/* ... Otherwise out of the overflow area. */
t = ovf;
! if (size < UNITS_PER_LONG)
t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
! size_int (UNITS_PER_LONG - size));
gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
*************** s390_function_profiler (FILE *file, int
*** 9002,9008 ****
op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
! op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
op[2] = gen_rtx_REG (Pmode, 1);
op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
--- 9038,9044 ----
op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
! op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
op[2] = gen_rtx_REG (Pmode, 1);
op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
*************** s390_call_saved_register_used (tree call
*** 9408,9421 ****
s390_function_arg_advance (&cum, mode, type, 0);
! if (parm_rtx && REG_P (parm_rtx))
{
! for (reg = 0;
! reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
! reg++)
! if (! call_used_regs[reg + REGNO (parm_rtx)])
! return true;
}
}
return false;
}
--- 9444,9493 ----
s390_function_arg_advance (&cum, mode, type, 0);
! if (!parm_rtx)
! continue;
!
! if (REG_P (parm_rtx))
! {
! int n_regs;
!
! /* Only integer registers (r6) are call saved and used for
! parameter passing. */
! if (REGNO_REG_CLASS (REGNO (parm_rtx)) == FP_REGS)
! continue;
!
! n_regs = ((GET_MODE_SIZE (GET_MODE (parm_rtx)) + UNITS_PER_LONG - 1)
! / UNITS_PER_LONG);
!
! for (reg = 0; reg < n_regs; reg++)
! if (!call_used_regs[reg + REGNO (parm_rtx)])
! return true;
! }
!
! if (GET_CODE (parm_rtx) == PARALLEL)
{
! int i;
! for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
! {
! rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
! int n_regs;
!
! gcc_assert (REG_P (r));
!
! /* Only integer registers (r6) are call saved and used
! for parameter passing. */
! if (REGNO_REG_CLASS (REGNO (r)) == FP_REGS)
! continue;
!
! n_regs = ((GET_MODE_SIZE (GET_MODE (r)) + UNITS_PER_LONG - 1)
! / UNITS_PER_LONG);
!
! for (reg = 0; reg < n_regs; reg++)
! if (!call_used_regs[reg + REGNO (r)])
! return true;
! }
}
+
}
return false;
}
*************** s390_optimize_prologue (void)
*** 9661,9667 ****
{
new_insn = save_gprs (base,
off + (cfun_frame_layout.first_save_gpr
! - first) * UNITS_PER_WORD,
cfun_frame_layout.first_save_gpr,
cfun_frame_layout.last_save_gpr);
new_insn = emit_insn_before (new_insn, insn);
--- 9733,9739 ----
{
new_insn = save_gprs (base,
off + (cfun_frame_layout.first_save_gpr
! - first) * UNITS_PER_LONG,
cfun_frame_layout.first_save_gpr,
cfun_frame_layout.last_save_gpr);
new_insn = emit_insn_before (new_insn, insn);
*************** s390_optimize_prologue (void)
*** 9722,9728 ****
{
new_insn = restore_gprs (base,
off + (cfun_frame_layout.first_restore_gpr
! - first) * UNITS_PER_WORD,
cfun_frame_layout.first_restore_gpr,
cfun_frame_layout.last_restore_gpr);
new_insn = emit_insn_before (new_insn, insn);
--- 9794,9800 ----
{
new_insn = restore_gprs (base,
off + (cfun_frame_layout.first_restore_gpr
! - first) * UNITS_PER_LONG,
cfun_frame_layout.first_restore_gpr,
cfun_frame_layout.last_restore_gpr);
new_insn = emit_insn_before (new_insn, insn);
*************** s390_loop_unroll_adjust (unsigned nunrol
*** 10319,10330 ****
--- 10391,10406 ----
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
+
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION s390_handle_option
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
+ #undef TARGET_SCALAR_MODE_SUPPORTED_P
+ #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
+
#ifdef HAVE_AS_TLS
#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS true
*************** s390_loop_unroll_adjust (unsigned nunrol
*** 10438,10443 ****
--- 10514,10522 ----
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT s390_trampoline_init
+ #undef TARGET_UNWIND_WORD_MODE
+ #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-s390.h"
Index: gcc/longlong.h
===================================================================
*** gcc/longlong.h.orig
--- gcc/longlong.h
*************** UDItype __umulsidi3 (USItype, USItype);
*** 318,323 ****
--- 318,324 ----
#endif
#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
+ #if !defined (__zarch__)
#define smul_ppmm(xh, xl, m0, m1) \
do { \
union {DItype __ll; \
*************** UDItype __umulsidi3 (USItype, USItype);
*** 339,344 ****
--- 340,367 ----
: "0" (__x.__ll), "r" (d)); \
(q) = __x.__i.__l; (r) = __x.__i.__h; \
} while (0)
+ #else
+ #define smul_ppmm(xh, xl, m0, m1) \
+ do { \
+ register SItype r0 __asm__ ("0"); \
+ register SItype r1 __asm__ ("1") = m0; \
+ \
+ __asm__ ("mr\t%%r0,%3" \
+ : "=r" (r0), "=r" (r1) \
+ : "r" (r1), "r" (m1)); \
+ (xh) = r1; (xl) = r0; \
+ } while (0)
+ #define sdiv_qrnnd(q, r, n1, n0, d) \
+ do { \
+ register SItype r0 __asm__ ("0") = n0; \
+ register SItype r1 __asm__ ("1") = n1; \
+ \
+ __asm__ ("dr\t%%r0,%3" \
+ : "=r" (r0), "=r" (r1) \
+ : "r" (r0), "r" (r1), "r" (d)); \
+ (q) = r0; (r) = r1; \
+ } while (0)
+ #endif /* __zarch__ */
#endif
#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
Index: gcc/config/s390/s390.h
===================================================================
*** gcc/config/s390/s390.h.orig
--- gcc/config/s390/s390.h
*************** extern int s390_arch_flags;
*** 108,113 ****
--- 108,115 ----
builtin_assert ("cpu=s390"); \
builtin_assert ("machine=s390"); \
builtin_define ("__s390__"); \
+ if (TARGET_ZARCH) \
+ builtin_define ("__zarch__"); \
if (TARGET_64BIT) \
builtin_define ("__s390x__"); \
if (TARGET_LONG_DOUBLE_128) \
*************** extern int s390_arch_flags;
*** 185,201 ****
#define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \
| S390_TDC_NEGATIVE_INFINITY )
- /* In libgcc2, determine target settings as compile-time constants. */
- #ifdef IN_LIBGCC2
- #undef TARGET_64BIT
- #ifdef __s390x__
- #define TARGET_64BIT 1
- #else
- #define TARGET_64BIT 0
- #endif
- #endif
-
-
/* Target machine storage layout. */
/* Everything is big-endian. */
--- 187,192 ----
*************** extern int s390_arch_flags;
*** 203,214 ****
#define BYTES_BIG_ENDIAN 1
#define WORDS_BIG_ENDIAN 1
! /* Width of a word, in units (bytes). */
! #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
#ifndef IN_LIBGCC2
! #define MIN_UNITS_PER_WORD 4
#endif
! #define MAX_BITS_PER_WORD 64
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
#define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
--- 194,226 ----
#define BYTES_BIG_ENDIAN 1
#define WORDS_BIG_ENDIAN 1
! #define STACK_SIZE_MODE (Pmode)
!
#ifndef IN_LIBGCC2
!
! /* Width of a word, in units (bytes). */
! #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4)
!
! /* Width of a pointer. To be used instead of UNITS_PER_WORD in
! ABI-relevant contexts. This always matches
! GET_MODE_SIZE (Pmode). */
! #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4)
! #define MIN_UNITS_PER_WORD 4
! #define MAX_BITS_PER_WORD 64
! #else
!
! /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether
! the library should export TImode functions or not. Thus, we have
! to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */
! #ifdef __s390x__
! #define UNITS_PER_WORD 8
! #else
! #define UNITS_PER_WORD 4
! #endif
#endif
!
! /* Width of a pointer, in bits. */
! #define POINTER_SIZE (TARGET_64BIT ? 64 : 32)
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
#define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
*************** extern int s390_arch_flags;
*** 402,407 ****
--- 414,428 ----
(((MODE1) == SFmode || (MODE1) == DFmode) \
== ((MODE2) == SFmode || (MODE2) == DFmode))
+ /* When generating code that runs in z/Architecture mode,
+ but conforms to the 31-bit ABI, GPRs can hold 8 bytes;
+ the ABI guarantees only that the lower 4 bytes are
+ saved across calls, however. */
+ #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
+ (!TARGET_64BIT && TARGET_ZARCH \
+ && GET_MODE_SIZE (MODE) > 4 \
+ && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32))
+
/* Maximum number of registers to represent a value of mode MODE
in a register of class CLASS. */
#define CLASS_MAX_NREGS(CLASS, MODE) \
*************** extern const enum reg_class regclass_map
*** 573,579 ****
the corresponding RETURN_REGNUM register was saved. */
#define DYNAMIC_CHAIN_ADDRESS(FRAME) \
(TARGET_PACKED_STACK ? \
! plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_WORD) : (FRAME))
/* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of
builtin_frame_address. Otherwise arg pointer -
--- 594,600 ----
the corresponding RETURN_REGNUM register was saved. */
#define DYNAMIC_CHAIN_ADDRESS(FRAME) \
(TARGET_PACKED_STACK ? \
! plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME))
/* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of
builtin_frame_address. Otherwise arg pointer -
*************** extern const enum reg_class regclass_map
*** 609,614 ****
--- 630,638 ----
? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
: DW_EH_PE_absptr)
+ /* Register save slot alignment. */
+ #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG)
+
/* Frame registers. */
*************** do { \
*** 790,808 ****
/* The maximum number of bytes that a single instruction can move quickly
between memory and registers or between two memory locations. */
! #define MOVE_MAX (TARGET_64BIT ? 16 : 8)
! #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
#define MAX_MOVE_MAX 16
/* Determine whether to use move_by_pieces or block move insn. */
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
! || (TARGET_64BIT && (SIZE) == 8) )
/* Determine whether to use clear_by_pieces or block clear insn. */
#define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
! || (TARGET_64BIT && (SIZE) == 8) )
/* This macro is used to determine whether store_by_pieces should be
called to "memcpy" storage when the source is a constant string. */
--- 814,832 ----
/* The maximum number of bytes that a single instruction can move quickly
between memory and registers or between two memory locations. */
! #define MOVE_MAX (TARGET_ZARCH ? 16 : 8)
! #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4)
#define MAX_MOVE_MAX 16
/* Determine whether to use move_by_pieces or block move insn. */
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
! || (TARGET_ZARCH && (SIZE) == 8) )
/* Determine whether to use clear_by_pieces or block clear insn. */
#define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
! || (TARGET_ZARCH && (SIZE) == 8) )
/* This macro is used to determine whether store_by_pieces should be
called to "memcpy" storage when the source is a constant string. */
*************** do { \
*** 907,913 ****
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
do { \
char buf[32]; \
! fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
assemble_name ((FILE), buf); \
fputc ('\n', (FILE)); \
--- 931,937 ----
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
do { \
char buf[32]; \
! fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \
ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
assemble_name ((FILE), buf); \
fputc ('\n', (FILE)); \
*************** do { \
*** 917,923 ****
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
do { \
char buf[32]; \
! fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
assemble_name ((FILE), buf); \
fputc ('-', (FILE)); \
--- 941,947 ----
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
do { \
char buf[32]; \
! fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \
ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
assemble_name ((FILE), buf); \
fputc ('-', (FILE)); \
Index: libjava/include/s390-signal.h
===================================================================
*** libjava/include/s390-signal.h.orig
--- libjava/include/s390-signal.h
*************** static void _name (int, siginfo_t *_si _
*** 39,44 ****
--- 39,45 ----
and if dividend and divisor are as above, we simply return from the signal
handler. This causes execution to continue after the instruction.
Before returning, we the set result registers as expected. */
+ #define UC_EXTENDED 0x00000001
#define HANDLE_DIVIDE_OVERFLOW \
do \
*************** do \
*** 47,52 ****
--- 48,62 ----
__builtin_extract_return_addr (_si->si_addr); \
unsigned long *_regs = _uc->uc_mcontext.gregs; \
int _r1, _r2, _d2, _x2, _b2; \
+ struct \
+ { \
+ unsigned long int uc_flags; \
+ struct ucontext *uc_link; \
+ stack_t uc_stack; \
+ mcontext_t uc_mcontext; \
+ unsigned long sigmask[2]; \
+ unsigned long ext_regs[16]; \
+ } *_uc_ext = (typeof(_uc_ext))_uc; \
\
/* First, a couple of helper routines to decode instructions. */ \
struct _decode \
*************** do \
*** 119,126 ****
{ \
return _d + (_x? _regs[_x] : 0) + (_b? _regs[_b] : 0); \
} \
- }; \
\
\
/* DR r1,r2 */ \
if (_decode::_is_rr (_eip, 0x1d, &_r1, &_r2) \
--- 129,144 ----
{ \
return _d + (_x? _regs[_x] : 0) + (_b? _regs[_b] : 0); \
} \
\
+ static inline int is_long_long_min_p (unsigned long *_regs, \
+ unsigned long *_ext_regs, \
+ int _r) \
+ { \
+ return ((long long)_regs[_r] \
+ | (long long)_ext_regs[_r] << 32) == \
+ LONG_LONG_MIN; \
+ } \
+ }; \
\
/* DR r1,r2 */ \
if (_decode::_is_rr (_eip, 0x1d, &_r1, &_r2) \
*************** do \
*** 175,182 ****
_regs[_r1] = 0; \
return; \
} \
! \
! } \
while (0)
/* For an explanation why we cannot simply use sigaction to
--- 193,250 ----
_regs[_r1] = 0; \
return; \
} \
! \
! /* The extended ucontext contains the upper halfs of the 64bit \
! registers in 31bit applications. */ \
! if (_uc->uc_flags & 1 == 1) \
! { \
! /* DSGR r1,r2 */ \
! if (_decode::_is_rre (_eip, 0xb9, 0x0d, &_r1, &_r2) \
! && (int) _regs[_r2] == -1 \
! && (int) _uc_ext->ext_regs[_r2] == -1 \
! && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs, \
! _r1 + 1)) \
! { \
! _regs[_r1] = 0; \
! _uc_ext->ext_regs[_r1] = 0; \
! return; \
! } \
! \
! /* DSGFR r1,r2 */ \
! if (_decode::_is_rre (_eip, 0xb9, 0x1d, &_r1, &_r2) \
! && (int) _regs[_r2] == -1 \
! && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs, \
! _r1 + 1)) \
! { \
! _regs[_r1] = 0; \
! _uc_ext->ext_regs[_r1] = 0; \
! return; \
! } \
! \
! /* DSG r1,d2(x2,b2) */ \
! if (_decode::_is_rxy (_eip, 0xe3, 0x0d, &_r1, &_d2, &_x2, &_b2) \
! && *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1 \
! && *(int *) _decode::_eff (_regs, _d2 + 4, _x2, _b2) == -1 \
! && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs, \
! _r1 + 1)) \
! { \
! _regs[_r1] = 0; \
! _uc_ext->ext_regs[_r1] = 0; \
! return; \
! } \
! \
! /* DSGF r1,d2(x2,b2) */ \
! if (_decode::_is_rxy (_eip, 0xe3, 0x1d, &_r1, &_d2, &_x2, &_b2) \
! && *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1 \
! && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs, \
! _r1 + 1)) \
! { \
! _regs[_r1] = 0; \
! _uc_ext->ext_regs[_r1] = 0; \
! return; \
! } \
! } \
! } \
while (0)
/* For an explanation why we cannot simply use sigaction to