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[Patch ARM] Fix PR43698.


Hi, 

This patch fixes PR43698. The problem essentially was that
arm_final_prescan_insn was happily going ahead and conditionalizing an
instruction that wasn't predicable. I've still not completely worked
through the logic of the ccfsm state machine in this case but this
obvious patch seems to fix the issue.

I'm currently running a full test on v7-a/-mthumb and v6/-mthumb on gcc
4.5 branch and trunk to make sure there are no regressions by this
patch. 

Ok to commit to trunk and gcc 4.5 branch if no regressions ?

cheers
Ramana

2010-04-09  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/43698
	* config/arm/arm.md: Split into 32 bit and Thumb1 variants.

2010-04-09  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gcc.target/arm/pr43698.c: New.




--- /dev//null	2010-04-03 00:33:59.311153460 +0100
+++ ./pr43698.c	2010-04-09 09:31:12.000000000 +0100
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-Os" } */
+
+#include <stdint.h>
+#include <stdlib.h>
+
+char do_reverse_endian = 0;
+
+#  define bswap_32(x) \
+  ((((x) & 0xff000000) >> 24) | \
+   (((x) & 0x00ff0000) >>  8) | \
+   (((x) & 0x0000ff00) <<  8) | \
+   (((x) & 0x000000ff) << 24))
+
+#define EGET(X) \
+  (__extension__ ({ \
+      uint64_t __res; \
+      if (!do_reverse_endian) {    __res = (X); \
+      } else if (sizeof(X) == 4) { __res = bswap_32((X)); \
+      } \
+      __res; \
+    }))
+
+void __attribute__((noinline)) X(char **phdr, char **data, int *phoff)
+{
+  *phdr = *data + EGET(*phoff);
+}
+
+int main()
+{
+  char *phdr;
+  char *data = (char *)0x40164000;
+  int phoff = 0x34;
+  X(&phdr, &data, &phoff);
+  if (phdr != (char *)0x40164034)
+    abort ();
+  exit (0);
+}
Index: arm.md
===================================================================
--- arm.md	(revision 158138)
+++ arm.md	(working copy)
@@ -11200,12 +11200,18 @@
 (define_insn "arm_rev"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
 	(bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
-  "TARGET_EITHER && arm_arch6"
+  "TARGET_32BIT && arm_arch6"
+  "rev%?\t%0, %1"
+  [(set_attr "predicable" "yes")
+   (set_attr "length" "4")]
+)
+
+(define_insn "thumb1_rev"
+  [(set (match_operand:SI 0 "s_register_operand" "=l")
+	(bswap:SI (match_operand:SI 1 "s_register_operand" "l")))]
+  "TARGET_THUMB1 && arm_arch6"
   "rev\t%0, %1"
-  [(set (attr "length")
-        (if_then_else (eq_attr "is_thumb" "yes")
-		      (const_int 2)
-		      (const_int 4)))]
+  [(set_attr "length" "2")]
 )
 
 (define_expand "arm_legacy_rev"

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