WIP patch, RFC: ARM ldm/stm peephole rewrite

[Bernd Schmidt <bernds at codesourcery dot com>]

This is a work-in-progress patch.  I'm posting it in the hope of getting
early feedback from the ARM maintainers.

The motivation for this patch is to be able to generate ldm/stm insns in
Thumb mode, where ldmia/stmia always update the base register.  To do
this, it helps to be able to use peep2_reg_dead_p, so the peepholes need
to be converted to define_peephole2.  In the future, some other
peepholes I plan to write could use peephole2's mechanism to allocate
free registers.

Not all forms of ldm/stm can be represented by existing patterns, and
since there's a lot of them I've written a small generator program.

In several places, the code to generate ldm/stm instructions is guarded
by TARGET_ARM.  I've left this in place, but shouldn't it be TARGET_32BIT?

The patch depends on the three bug fixes I've posted previously:
  http://gcc.gnu.org/ml/gcc-patches/2010-03/msg01160.html
  http://gcc.gnu.org/ml/gcc-patches/2010-03/msg01161.html
  http://gcc.gnu.org/ml/gcc-patches/2010-03/msg01162.html

In the last test run, the results were mostly good, but I've identified
another bug, this time in loop-invariant.c, which breaks match_dups.
I'm currently testing a fix for that.


Bernd

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