Re: PATCH: Add LWP support for upcoming AMD Orochi processor.

[Sebastian Pop <sebpop at gmail dot com>]

On Thu, Dec 10, 2009 at 14:06, Jakub Jelinek <jakub@redhat.com> wrote:
> Why do you want the HI mode version generated, ever (except for 16-bit code which
> gcc doesn't emit)? ÂIMNSHO you don't want to ever use even the 32-bit one
> for -m64 code. ÂI believe you want lwpintrin.h to provide one intrinsic,
> not three, it takes a void * argument anyway in all 3 cases. ÂWhat would be
> an intrinsic that just uses some lower bits from the pointer good for?
> Why should a user care whether the pointer is 32-bit or 64-bit or 16-bit?
>
> What could make some very limited sense is when that void * pointer is
> initialized through say movl symbol, %edx use the 32-bit insn even for -m64
> code to save one byte, but 1) I doubt it is worth writing the peepholes
> 2) you don't want to let the user make this decision, instead you want the
> compiler to decide (if at all). ÂAnd 16-bit addresses aren't really useful
> at all.

Ok.  I simplified the lwpintrin.h file and the LWP insns patterns like this.

Sebastian

From 51d25a33c341f310f67c04d27ef69e0036bcae80 Mon Sep 17 00:00:00 2001
From: Sebastian Pop <sebpop@gmail.com>
Date: Thu, 10 Dec 2009 14:59:51 -0600
Subject: [PATCH] LWP factor insn patterns.

---
 gcc/config/i386/i386.c      |    4 --
 gcc/config/i386/i386.md     |   70 ++++---------------------------------------
 gcc/config/i386/lwpintrin.h |   46 ++++------------------------
 3 files changed, 13 insertions(+), 107 deletions(-)

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index f78cfa7..5002654 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -21532,18 +21532,14 @@ static const struct builtin_description bdesc_special_args[] =
   { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
   { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
 
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbhi1,   "__builtin_ia32_llwpcb16",   IX86_BUILTIN_LLWPCB16,    UNKNOWN,     (int) VOID_FTYPE_PCVOID },
   { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbsi1,   "__builtin_ia32_llwpcb32",   IX86_BUILTIN_LLWPCB32,    UNKNOWN,     (int) VOID_FTYPE_PCVOID },
   { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbdi1,   "__builtin_ia32_llwpcb64",   IX86_BUILTIN_LLWPCB64,    UNKNOWN,     (int) VOID_FTYPE_PCVOID },
 
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbhi1,   "__builtin_ia32_slwpcb16",   IX86_BUILTIN_SLWPCB16,    UNKNOWN,     (int) PCVOID_FTYPE_VOID },
   { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbsi1,   "__builtin_ia32_slwpcb32",   IX86_BUILTIN_SLWPCB32,    UNKNOWN,     (int) PCVOID_FTYPE_VOID },
   { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbdi1,   "__builtin_ia32_slwpcb64",   IX86_BUILTIN_SLWPCB64,    UNKNOWN,     (int) PCVOID_FTYPE_VOID },
 
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalhi3,   "__builtin_ia32_lwpval16", IX86_BUILTIN_LWPVAL16,  UNKNOWN,     (int) VOID_FTYPE_USHORT_UINT_USHORT },
   { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3,   "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32,  UNKNOWN,     (int) VOID_FTYPE_UINT_UINT_UINT },
   { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3,   "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64,  UNKNOWN,     (int) VOID_FTYPE_UINT64_UINT_UINT },
-  { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinshi3,   "__builtin_ia32_lwpins16", IX86_BUILTIN_LWPINS16,  UNKNOWN,     (int) UCHAR_FTYPE_USHORT_UINT_USHORT },
   { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3,   "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32,  UNKNOWN,     (int) UCHAR_FTYPE_UINT_UINT_UINT },
   { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3,   "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64,  UNKNOWN,     (int) UCHAR_FTYPE_UINT64_UINT_UINT },
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 0db4cbb..a8cbafa 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -20835,14 +20835,6 @@
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(define_insn "lwp_llwpcbhi1"
-  [(unspec_volatile [(match_operand:HI 0 "register_operand" "r")]
-  	   	    UNSPECV_LLWP_INTRINSIC)]
-  "TARGET_LWP"
-  "llwpcb\t%0"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "HI")])
-
 (define_insn "lwp_llwpcb<mode>1"
   [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
   	   	    UNSPECV_LLWP_INTRINSIC)]
@@ -20851,14 +20843,6 @@
   [(set_attr "type" "lwp")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "lwp_slwpcbhi1"
-  [(unspec [(match_operand:HI 0 "register_operand" "=r")]
-  	   UNSPEC_SLWP_INTRINSIC)]
-  "TARGET_LWP"
-  "slwpcb\t%0"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "HI")])
-
 (define_insn "lwp_slwpcb<mode>1"
   [(unspec [(match_operand:P 0 "register_operand" "=r")]
   	   UNSPEC_SLWP_INTRINSIC)]
@@ -20867,60 +20851,18 @@
   [(set_attr "type" "lwp")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "lwp_lwpvalhi3"
-  [(unspec_volatile [(match_operand:HI 0 "register_operand" "r")
-  	   	     (match_operand:SI 1 "nonimmediate_operand" "rm")
-		     (match_operand:HI 2 "const_int_operand" "i")]
-  	   	    UNSPECV_LWPVAL_INTRINSIC)]
-  "TARGET_LWP"
-  "lwpval\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "HI")])
-
-(define_insn "lwp_lwpvalsi3"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
+(define_insn "lwp_lwpval<mode>3"
+  [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")
     	    	     (match_operand:SI 1 "nonimmediate_operand" "rm")
 		     (match_operand:SI 2 "const_int_operand" "i")]
 		    UNSPECV_LWPVAL_INTRINSIC)]
   "TARGET_LWP"
   "lwpval\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "lwp")
-   (set_attr "mode" "SI")])
-
-(define_insn "lwp_lwpvaldi3"
-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
-  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
-		     (match_operand:SI 2 "const_int_operand" "i")]
-		    UNSPECV_LWPVAL_INTRINSIC)]
-  "TARGET_LWP"
-  "lwpval\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "DI")])
-
-(define_insn "lwp_lwpinshi3"
-  [(unspec_volatile [(match_operand:HI 0 "register_operand" "r")
-  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
-		     (match_operand:HI 2 "const_int_operand" "i")]
-		    UNSPECV_LWPINS_INTRINSIC)
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_LWP"
-  "lwpins\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "HI")])
-
-(define_insn "lwp_lwpinssi3"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
-  		     (match_operand:SI 1 "nonimmediate_operand" "rm")
-		     (match_operand:SI 2 "const_int_operand" "i")]
-		    UNSPECV_LWPINS_INTRINSIC)
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_LWP"
-  "lwpins\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "lwp")
-   (set_attr "mode" "SI")])
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "lwp_lwpinsdi3"
-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
+(define_insn "lwp_lwpins<mode>3"
+  [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")
   		     (match_operand:SI 1 "nonimmediate_operand" "rm")
 		     (match_operand:SI 2 "const_int_operand" "i")]
 		    UNSPECV_LWPINS_INTRINSIC)
@@ -20928,7 +20870,7 @@
   "TARGET_LWP"
   "lwpins\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "lwp")
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "<MODE>")])
 
 (include "mmx.md")
 (include "sse.md")
diff --git a/gcc/config/i386/lwpintrin.h b/gcc/config/i386/lwpintrin.h
index 50ce2ff..7f3ea8f 100644
--- a/gcc/config/i386/lwpintrin.h
+++ b/gcc/config/i386/lwpintrin.h
@@ -33,50 +33,25 @@
 #else
 
 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__llwpcb16 (void const *pcbAddress)
+__llwpcb (void const *pcbAddress)
 {
-  __builtin_ia32_llwpcb16 (pcbAddress);
-}
-
-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__llwpcb32 (void const *pcbAddress)
-{
-  __builtin_ia32_llwpcb32 (pcbAddress);
-}
-
 #ifdef __x86_64__
-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__llwpcb64 (void const *pcbAddress)
-{
   __builtin_ia32_llwpcb64 (pcbAddress);
-}
+#else
+  __builtin_ia32_llwpcb32 (pcbAddress);
 #endif
-
-extern __inline void const * __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__slwpcb16 (void)
-{
-  return __builtin_ia32_slwpcb16 ();
 }
 
 extern __inline void const * __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__slwpcb32 (void)
+__slwpcb (void)
 {
-  return __builtin_ia32_slwpcb32 ();
-}
-
 #ifdef __x86_64__
-extern __inline void const * __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__slwpcb64 (void)
-{
   return __builtin_ia32_slwpcb64 ();
-}
+#else
+  return __builtin_ia32_slwpcb32 ();
 #endif
-
-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__lwpval16 (unsigned short data2, unsigned int data1, unsigned short flags)
-{
-  __builtin_ia32_lwpval16 (data2, data1, flags);
 }
+
 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 __lwpval32 (unsigned int data2, unsigned int data1, unsigned int flags)
 {
@@ -91,12 +66,6 @@ __lwpval64 (unsigned long long data2, unsigned int data1, unsigned int flags)
 }
 #endif
 
-/*
-extern __inline unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-__lwpins16 (unsigned short data2, unsigned int data1, unsigned short flags)
-{
-  return __builtin_ia32_lwpins16 (data2, data1, flags);
-}
 
 extern __inline unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 __lwpins32 (unsigned int data2, unsigned int data1, unsigned int flags)
@@ -111,7 +80,6 @@ __lwpins64 (unsigned long long data2, unsigned int data1, unsigned int flags)
   return __builtin_ia32_lwpins64 (data2, data1, flags);
 }
 #endif
-*/
 
 #endif /* __LWP__ */
 
-- 
1.6.0.4