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[ARM] Fix PR target/42031
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: gcc patches <gcc-patches at gcc dot gnu dot org>
- Date: Sat, 14 Nov 2009 18:24:43 +0000
- Subject: [ARM] Fix PR target/42031
Hmm, I was sure that we used not to run the sched-1 pass when optimizing
for space, but I can't find anything to confirm whether or not this has
changed -- we certainly seem to have done so for a number of years now.
However,
This patch fixes a bug in the thumb-2 port when scheduling is enabled at
-Os prior to register allocation. It turns out that we have the
constraints in a sub-optimal order that causes reload to be stressed
more than it can handle. By putting the tied version first we can
usually get away with fewer reloads than otherwise and this not only
fixes the ICE but gives us slightly better code overall. I've tried to
find all the patterns that have similar behaviour and fix those too.
tested on arm-elf and committed to trunk
2009-11-14 Richard Earnshaw <rearnsha@arm.com>
PR target/42031
* arm.md (adddi_sesidi_di): Place tied contraint first.
(adddi_zesidi_di, subdi_di_zesidi, subdi_di_sesidi): Likewise
(subdi_zesidi_di, subdi_sesidi_di): Likewise.
(mulsi3_compare0, mulsi_compare0_scratch): Likewise.
(mulsi3addsi, mulsi3addsi_compare0): Likewise.
(mulsi3addsi_compare0_scratch, smulsi3_highpart_nov6): Likewise.
(umulsi3_highpart_nov6, anddi_zesidi_di, anddi_sesdi_di): Likewise.
(anddi_notdi_di, iordi_sesidi_di, xordi_sesidi_di): Likewise.
(andsi_iorsi3_notsi, arm_ashldi3_1bit, arm_ashrdi3_1_bit): Likewise.
(arm_lshrdi3_1bit, one_cmpldi2): Likewise.
*** arm.md (revision 154170)
--- arm.md (local)
*************** (define_insn_and_split "*adddi_sesidi_di
*** 523,529 ****
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(plus:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "r,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
"#"
--- 523,529 ----
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(plus:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "0,r")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
"#"
*************** (define_insn_and_split "*adddi_zesidi_di
*** 552,558 ****
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(plus:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "r,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
"#"
--- 552,558 ----
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(plus:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "0,r")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
"#"
*************** (define_insn "*thumb_subdi3"
*** 1015,1021 ****
(define_insn "*subdi_di_zesidi"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
! (minus:DI (match_operand:DI 1 "s_register_operand" "?r,0")
(zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))))
(clobber (reg:CC CC_REGNUM))]
--- 1015,1021 ----
(define_insn "*subdi_di_zesidi"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
! (minus:DI (match_operand:DI 1 "s_register_operand" "0,r")
(zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))))
(clobber (reg:CC CC_REGNUM))]
*************** (define_insn "*subdi_di_zesidi"
*** 1027,1033 ****
(define_insn "*subdi_di_sesidi"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
! (minus:DI (match_operand:DI 1 "s_register_operand" "r,0")
(sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))))
(clobber (reg:CC CC_REGNUM))]
--- 1027,1033 ----
(define_insn "*subdi_di_sesidi"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
! (minus:DI (match_operand:DI 1 "s_register_operand" "0,r")
(sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))))
(clobber (reg:CC CC_REGNUM))]
*************** (define_insn "*subdi_zesidi_di"
*** 1041,1047 ****
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(minus:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "?r,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0"
--- 1041,1047 ----
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(minus:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "0,r")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0"
*************** (define_insn "*subdi_sesidi_di"
*** 1053,1059 ****
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(minus:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "?r,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31"
--- 1053,1059 ----
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(minus:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "0,r")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31"
*************** (define_expand "mulsi3"
*** 1222,1228 ****
(define_insn "*arm_mulsi3"
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
(mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
! (match_operand:SI 1 "s_register_operand" "%?r,0")))]
"TARGET_32BIT && !arm_arch6"
"mul%?\\t%0, %2, %1"
[(set_attr "insn" "mul")
--- 1222,1228 ----
(define_insn "*arm_mulsi3"
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
(mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
! (match_operand:SI 1 "s_register_operand" "%0,r")))]
"TARGET_32BIT && !arm_arch6"
"mul%?\\t%0, %2, %1"
[(set_attr "insn" "mul")
*************** (define_insn "*mulsi3_compare0"
*** 1276,1282 ****
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
! (match_operand:SI 1 "s_register_operand" "%?r,0"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
(mult:SI (match_dup 2) (match_dup 1)))]
--- 1276,1282 ----
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
! (match_operand:SI 1 "s_register_operand" "%0,r"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
(mult:SI (match_dup 2) (match_dup 1)))]
*************** (define_insn "*mulsi_compare0_scratch"
*** 1304,1310 ****
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
! (match_operand:SI 1 "s_register_operand" "%?r,0"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=&r,&r"))]
"TARGET_ARM && !arm_arch6"
--- 1304,1310 ----
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r")
! (match_operand:SI 1 "s_register_operand" "%0,r"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=&r,&r"))]
"TARGET_ARM && !arm_arch6"
*************** (define_insn "*mulsi3addsi"
*** 1332,1339 ****
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
(plus:SI
(mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")
! (match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
! (match_operand:SI 3 "s_register_operand" "?r,r,0,0")))]
"TARGET_32BIT && !arm_arch6"
"mla%?\\t%0, %2, %1, %3"
[(set_attr "insn" "mla")
--- 1332,1339 ----
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
(plus:SI
(mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")
! (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
! (match_operand:SI 3 "s_register_operand" "r,r,0,0")))]
"TARGET_32BIT && !arm_arch6"
"mla%?\\t%0, %2, %1, %3"
[(set_attr "insn" "mla")
*************** (define_insn "*mulsi3addsi_compare0"
*** 1357,1364 ****
(compare:CC_NOOV
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
! (match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
! (match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
(plus:SI (mult:SI (match_dup 2) (match_dup 1))
--- 1357,1364 ----
(compare:CC_NOOV
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
! (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
! (match_operand:SI 3 "s_register_operand" "r,r,0,0"))
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
(plus:SI (mult:SI (match_dup 2) (match_dup 1))
*************** (define_insn "*mulsi3addsi_compare0_scra
*** 1391,1397 ****
(compare:CC_NOOV
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
! (match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
(match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
--- 1391,1397 ----
(compare:CC_NOOV
(plus:SI (mult:SI
(match_operand:SI 2 "s_register_operand" "r,r,r,r")
! (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
(match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
*************** (define_insn "*smulsi3_highpart_nov6"
*** 1571,1577 ****
(truncate:SI
(lshiftrt:DI
(mult:DI
! (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r,0"))
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=&r,&r"))]
--- 1571,1577 ----
(truncate:SI
(lshiftrt:DI
(mult:DI
! (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=&r,&r"))]
*************** (define_insn "*umulsi3_highpart_nov6"
*** 1615,1621 ****
(truncate:SI
(lshiftrt:DI
(mult:DI
! (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r,0"))
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=&r,&r"))]
--- 1615,1621 ----
(truncate:SI
(lshiftrt:DI
(mult:DI
! (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=&r,&r"))]
*************** (define_insn_and_split "*anddi_zesidi_di
*** 1870,1876 ****
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(and:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "?r,0")))]
"TARGET_32BIT"
"#"
"TARGET_32BIT && reload_completed"
--- 1870,1876 ----
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(and:DI (zero_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "0,r")))]
"TARGET_32BIT"
"#"
"TARGET_32BIT && reload_completed"
*************** (define_insn "*anddi_sesdi_di"
*** 1891,1897 ****
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(and:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "?r,0")))]
"TARGET_32BIT"
"#"
[(set_attr "length" "8")]
--- 1891,1897 ----
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(and:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "0,r")))]
"TARGET_32BIT"
"#"
[(set_attr "length" "8")]
*************** (define_insn "insv_t2"
*** 2457,2464 ****
; constants for op 2 will never be given to these patterns.
(define_insn_and_split "*anddi_notdi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
! (and:DI (not:DI (match_operand:DI 1 "s_register_operand" "r,0"))
! (match_operand:DI 2 "s_register_operand" "0,r")))]
"TARGET_32BIT"
"#"
"TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
--- 2457,2464 ----
; constants for op 2 will never be given to these patterns.
(define_insn_and_split "*anddi_notdi_di"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
! (and:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
! (match_operand:DI 2 "s_register_operand" "r,0")))]
"TARGET_32BIT"
"#"
"TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
*************** (define_insn "*iordi_sesidi_di"
*** 2612,2618 ****
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(ior:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "?r,0")))]
"TARGET_32BIT"
"#"
[(set_attr "length" "8")
--- 2612,2618 ----
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(ior:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "0,r")))]
"TARGET_32BIT"
"#"
[(set_attr "length" "8")
*************** (define_insn "*xordi_sesidi_di"
*** 2742,2748 ****
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(xor:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "?r,0")))]
"TARGET_32BIT"
"#"
[(set_attr "length" "8")
--- 2742,2748 ----
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(xor:DI (sign_extend:DI
(match_operand:SI 2 "s_register_operand" "r,r"))
! (match_operand:DI 1 "s_register_operand" "0,r")))]
"TARGET_32BIT"
"#"
[(set_attr "length" "8")
*************** (define_split
*** 2836,2842 ****
(define_insn "*andsi_iorsi3_notsi"
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r")
! (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,0")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))
(not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))]
"TARGET_32BIT"
--- 2836,2842 ----
(define_insn "*andsi_iorsi3_notsi"
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r")
! (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "%0,r,r")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))
(not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))]
"TARGET_32BIT"
*************** (define_expand "ashldi3"
*** 3190,3196 ****
(define_insn "arm_ashldi3_1bit"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
! (ashift:DI (match_operand:DI 1 "s_register_operand" "?r,0")
(const_int 1)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
--- 3190,3196 ----
(define_insn "arm_ashldi3_1bit"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
! (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r")
(const_int 1)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
*************** (define_expand "ashrdi3"
*** 3249,3255 ****
(define_insn "arm_ashrdi3_1bit"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
! (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "?r,0")
(const_int 1)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
--- 3249,3255 ----
(define_insn "arm_ashrdi3_1bit"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
! (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
(const_int 1)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
*************** (define_expand "lshrdi3"
*** 3305,3311 ****
(define_insn "arm_lshrdi3_1bit"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
! (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "?r,0")
(const_int 1)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
--- 3305,3311 ----
(define_insn "arm_lshrdi3_1bit"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
! (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
(const_int 1)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
*************** (define_expand "negdi2"
*** 3552,3561 ****
)
;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
! ;; The second alternative is to allow the common case of a *full* overlap.
(define_insn "*arm_negdi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
! (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0"
--- 3552,3561 ----
)
;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
! ;; The first alternative allows the common case of a *full* overlap.
(define_insn "*arm_negdi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
! (neg:DI (match_operand:DI 1 "s_register_operand" "0,r")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM"
"rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0"
*************** (define_expand "sqrtdf2"
*** 3708,3714 ****
(define_insn_and_split "one_cmpldi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
! (not:DI (match_operand:DI 1 "s_register_operand" "?r,0")))]
"TARGET_32BIT"
"#"
"TARGET_32BIT && reload_completed"
--- 3708,3714 ----
(define_insn_and_split "one_cmpldi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
! (not:DI (match_operand:DI 1 "s_register_operand" "0,r")))]
"TARGET_32BIT"
"#"
"TARGET_32BIT && reload_completed"