Re: [PATCH: PR target/40835] Remove comparison with 0 after instruction movs for thumb

[Carrot Wei <carrot at google dot com>]

I've tested this patch without any new failure. If you agree I can
check in this patch and the new test case.

thanks
Wei Guozhi

On Sun, Nov 1, 2009 at 5:41 PM, Carrot Wei <carrot@google.com> wrote:
> Great! ?I didn't know there is an insn pattern "movsi_cbranchsi4" can
> be used. When will you check in this patch?
>
> thanks
> Wei Guozhi
>
>
> On Sat, Oct 31, 2009 at 9:38 PM, Richard Earnshaw <rearnsha@arm.com> wrote:
>>
>> On Sat, 2009-10-31 at 20:56 +0800, Carrot Wei wrote:
>>> You are right. Use sub can remove more cmp instructions. The patch
>>> has been updated to reflect this.
>>>
>>> Test:
>>> This patch was applied to trunk GCC and tested on the arm emulator with newlib.
>>> No new failure.
>>>
>>> ChangeLog:
>>> 2009-10-31 ?Wei Guozhi ?<carrot@google.com>
>>>
>>> ? ? ? ? PR target/40835
>>> ? ? ? ? * config/arm/arm.c (emit_branch_after_movs): New function.
>>> ? ? ? ? (removable_cmp_0): New function.
>>> ? ? ? ? * config/arm/arm-protos.h (emit_branch_after_movs): Declare it.
>>> ? ? ? ? (removable_cmp_0): Declare it.
>>> ? ? ? ? * config/arm/arm.md: Add peephole rule to do the optimization.
>>>
>>> 2009-10-31 ?Wei Guozhi ?<carrot@google.com>
>>>
>>> ? ? ? ? PR target/40835
>>> ? ? ? ? * gcc.target/arm/pr40835: New testcase.
>>>
>>
>> This is needlessly complicated. ?I've only tested the following by
>> examination, but it's a much more robust solution.
>>
>> Note I wouldn't normally condone adding peepholes for the second case
>> (where there's a natural data-flow dependency between the insns), but it
>> turns out that in this scenario combine is being prevented from
>> optimizing this case by the need to reduce register pressure and this is
>> common enough to warrant an exception.
>>
>> R.
>>
>