This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH: PR target/40835] Remove comparison with 0 after instruction movs for thumb


Great!  I didn't know there is an insn pattern "movsi_cbranchsi4" can
be used. When will you check in this patch?

thanks
Wei Guozhi


On Sat, Oct 31, 2009 at 9:38 PM, Richard Earnshaw <rearnsha@arm.com> wrote:
>
> On Sat, 2009-10-31 at 20:56 +0800, Carrot Wei wrote:
>> You are right. Use sub can remove more cmp instructions. The patch
>> has been updated to reflect this.
>>
>> Test:
>> This patch was applied to trunk GCC and tested on the arm emulator with newlib.
>> No new failure.
>>
>> ChangeLog:
>> 2009-10-31 ?Wei Guozhi ?<carrot@google.com>
>>
>> ? ? ? ? PR target/40835
>> ? ? ? ? * config/arm/arm.c (emit_branch_after_movs): New function.
>> ? ? ? ? (removable_cmp_0): New function.
>> ? ? ? ? * config/arm/arm-protos.h (emit_branch_after_movs): Declare it.
>> ? ? ? ? (removable_cmp_0): Declare it.
>> ? ? ? ? * config/arm/arm.md: Add peephole rule to do the optimization.
>>
>> 2009-10-31 ?Wei Guozhi ?<carrot@google.com>
>>
>> ? ? ? ? PR target/40835
>> ? ? ? ? * gcc.target/arm/pr40835: New testcase.
>>
>
> This is needlessly complicated. ?I've only tested the following by
> examination, but it's a much more robust solution.
>
> Note I wouldn't normally condone adding peepholes for the second case
> (where there's a natural data-flow dependency between the insns), but it
> turns out that in this scenario combine is being prevented from
> optimizing this case by the need to reduce register pressure and this is
> common enough to warrant an exception.
>
> R.
>


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]