[PATCH, ARM] Fix Dwarf register numbering for VFPv3/Neon registers

[Julian Brown <julian at codesourcery dot com>]

This patch fixes the Dwarf register numbering for VFPv3/NEON to better
match the ARM EABI. VFPv3 introduces new double-precision registers
(D16-D31). The EABI specifies that D0-D31 these should have Dwarf
numbers 256-287, and makes the old numbering obsolete.

However, to maintain compatibility with older debuggers, the old
numbering is still used for S0-S31 and D0-D15. (I'm not sure if the
ARM-recommended encoding for single-precision registers using
DW_OP_bit_piece of double-precision registers is supported by GDB yet).

Tested (gcc/g++/libstdc++) with cross to ARM EABI.

OK to apply?

Julian

ChangeLog

    Paul Brook  <paul@codesourcery.com>

    gcc/
    * config/arm/arm.c (TARGET_DWARF_REGISTER_SPAN): Define.
    (arm_dwarf_register_span): New function.
    (arm_dbx_register_number): Add VFPv3 dwarf numbering.

commit 3f2a2f848106a30a2af0a09f60c02fd7bbbdeb49
Author: Julian Brown <julian@verona.codesourcery.com>
Date:   Thu Oct 29 08:18:00 2009 -0700

    Fix VFPv3 register numbering for Dwarf.

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 35bd394..353f956 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -191,6 +191,7 @@ static void arm_unwind_emit (FILE *, rtx);
 static bool arm_output_ttype (rtx);
 #endif
 static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);
+static rtx arm_dwarf_register_span (rtx);
 
 static tree arm_cxx_guard_type (void);
 static bool arm_cxx_guard_mask_bit (void);
@@ -438,6 +439,9 @@ static const struct attribute_spec arm_attribute_table[] =
 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
 
+#undef TARGET_DWARF_REGISTER_SPAN
+#define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span
+
 #undef  TARGET_CANNOT_COPY_INSN_P
 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
 
@@ -20526,9 +20530,14 @@ arm_dbx_register_number (unsigned int regno)
   if (IS_FPA_REGNUM (regno))
     return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
 
-  /* FIXME: VFPv3 register numbering.  */
   if (IS_VFP_REGNUM (regno))
-    return 64 + regno - FIRST_VFP_REGNUM;
+    {
+      /* See comment in arm_dwarf_register_span.  */
+      if (VFP_REGNO_OK_FOR_SINGLE (regno))
+	return 64 + regno - FIRST_VFP_REGNUM;
+      else
+	return 256 + (regno - FIRST_VFP_REGNUM) / 2;
+    }
 
   if (IS_IWMMXT_GR_REGNUM (regno))
     return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
@@ -20539,6 +20548,40 @@ arm_dbx_register_number (unsigned int regno)
   gcc_unreachable ();
 }
 
+/* Dwarf models VFPv3 registers as 32 64-bit registers.
+   GCC models tham as 64 32-bit registers, so we need to describe this to
+   the DWARF generation code.  Other registers can use the default.  */
+
+static rtx
+arm_dwarf_register_span (rtx rtl)
+{
+  unsigned regno;
+  int nregs;
+  int i;
+  rtx p;
+
+  regno = REGNO (rtl);
+  if (!IS_VFP_REGNUM (regno))
+    return NULL_RTX;
+
+  /* The EABI defines two VFP register ranges:
+       64-95: Legacy VFPv2 numbering for S0-S31 (obsolescent)
+       256-287: D0-D31
+     The recommended encodings for S0-S31 is a DW_OP_bit_piece of the
+     corresponding D register.  However gdb6.6 does not support this, so
+     we use the legacy encodings.  We also use these encodings for D0-D15
+     for compatibility with older debuggers.  */
+  if (VFP_REGNO_OK_FOR_SINGLE (regno))
+    return NULL_RTX;
+
+  nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8;
+  p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
+  regno = (regno - FIRST_VFP_REGNUM) / 2;
+  for (i = 0; i < nregs; i++)
+    XVECEXP (p, 0, i) = gen_rtx_REG (DImode, 256 + regno + i);
+
+  return p;
+}
 
 #ifdef TARGET_UNWIND_INFO
 /* Emit unwind directives for a store-multiple instruction or stack pointer