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Re: [Patch] MIPS: Emit optimized sync instructions for Octeon CPUs.


David Daney <ddaney@caviumnetworks.com> writes:
> The Octeon CPU has a variant of the SYNC instruction called SYNCW that 
> is much faster when only ordering of writes is needed.  The built-in 
> atomic memory operations are one case where syncw may be used.

Sorry to have to ask, but why is that true for __sync_synchronize?
It's documented as being a full memory barrier.

A couple of minor formatting tweaks:

David Daney <ddaney@caviumnetworks.com> writes:
> Index: gcc/config/mips/sync.md
> ===================================================================
> --- gcc/config/mips/sync.md	(revision 150651)
> +++ gcc/config/mips/sync.md	(working copy)
> @@ -40,7 +40,10 @@ (define_insn "*memory_barrier"
>    [(set (match_operand:BLK 0 "" "")
>  	(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
>    "GENERATE_SYNC"
> -  "%|sync%-")
> +{
> +  return mips_output_sync_insn ();
> +}
> +  [(set (attr "length") (symbol_ref "mips_sync_insn_length ()"))])

{ return mips_output_sync_insn (); }

> +/* Return the length of code that would be emitted by
> +   mips_output_sync_loop(), given that the loop consists of LOOP_INSNS
> +   instructions and BARRIER_BEFORE has the same value as it would for
> +   mips_output_sync_loop.  */
> +
> +int
> +mips_sync_loop_length (bool barrier_before, int loop_insns)
> +{
> +  int sync_length = 0;
> +
> +  if (barrier_before)
> +    sync_length += mips_sync_insn_length ();
> +  if (TARGET_SYNC_AFTER_SC)
> +    sync_length += mips_sync_insn_length ();
> +  return (4 * loop_insns) + sync_length;
> +}
> +
> +/* Return or emit the assembly code for a SYNC instruction.  */
> +
> +const char *
> +mips_output_sync_insn (void)
> +{
> +  if (TARGET_OCTEON)
> +    {
> +      /*  For OCTEON, it is faster to issue two syncw instead of a
> +	  sync.*/
> +      return "syncw\n\tsyncw";
> +    }

  if (TARGET_OCTEON)
    /* For OCTEON, it is faster to issue two SYNCWs instead of a SYNC.  */
    return "syncw\n\tsyncw";

Richard


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