Re: PATCH PR target/40834: [4.5 Regression] standard_sse_constant_opcode crash on x86 64

[Uros Bizjak <ubizjak at gmail dot com>]

On 08/05/2009 08:01 PM, H.J. Lu wrote:

> There is no single AVX instruction to generate 256bit all 1s. This patch
> returns -3 on 256bit all 1s. OK for trunk?
>    

I think that following your change, there is a chance for substantial 
cleanup in this area:

- we can remove standard_sse_mode_p, since it is used only in one place 
(below).
- there is no need to complicate matters by returning negative values 
from standard_sse_constant_p. We either support "-1" as standard SSE 
constant or not.
- by using integer insn to start V4SF or V2DF insn stream, we risk SSE 
reformating penalty. And vector QNaN is definitely not _that_ usable to 
cover the risk.

Attached patch (tested in gcc.target/i386 and with a bunch of tests 
involving various _mm*_set1_epi* (-1) intrinsics) implements above points.

> --- gcc/testsuite/gcc.target/i386/pr40957.c.pr40957	2009-08-05 10:56:54.000000000 -0700
> +++ gcc/testsuite/gcc.target/i386/pr40957.c	2009-08-05 10:55:32.000000000 -0700
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target avx } */
> +/* { dg-options "-mavx -O" } */
> +
> +typedef int __v8si __attribute__ ((__vector_size__ (32)));
> +typedef long long __m256i __attribute__ ((__vector_size__ (32),
> +       __may_alias__));
> +extern __inline__ __m256i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_set1_epi32 (int __A)
> +{
> +  return __extension__ (__m256i)(__v8si){ __A, __A, __A, __A,
> +       __A, __A, __A, __A };
> +}
> +__m256i
> +foo ()
> +{
> +    __m256i ymm = _mm256_set1_epi32 (-1);
> +    asm volatile ("vmovdqa %0, %%ymm0" : : "x" (ymm) : "xmm0" );
> +  return ymm;
> +}
>    

Please remove asm from the testcase. You don't need it to trigger the break.

Thanks,
Uros.

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