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[mep] more intrinsic patches
- From: DJ Delorie <dj at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 8 Jul 2009 00:19:19 -0400
- Subject: [mep] more intrinsic patches
Continuing to tweak the intrinsics...
* config/mep/mep-ivc2.cpu (cpmovtocsar0_C3, cpmovtocsar1_C3,
cpmovtocc_C3, cpmovtocsar0_P0S_P1, cpmovtocsar1_P0S_P1,
cpmovtocc_P0S_P1): Mark volatile. Note which registers are
written to.
* config/mep/intrinsics.md: Regenerated.
* config/mep/mep.c (mep_interrupt_saved_reg): Save IVC2 control
registers when asm() or calls are detected.
Index: config/mep/mep.c
===================================================================
--- config/mep/mep.c (revision 149360)
+++ config/mep/mep.c (working copy)
@@ -2496,43 +2496,46 @@ mep_asm_without_operands_p (void)
/* Interrupt functions save/restore every call-preserved register, and
any call-used register it uses (or all if it calls any function,
since they may get clobbered there too). Here we check to see
which call-used registers need saving. */
+#define IVC2_ISAVED_REG(r) (TARGET_IVC2 \
+ && (r == FIRST_CCR_REGNO + 1 \
+ || (r >= FIRST_CCR_REGNO + 8 && r <= FIRST_CCR_REGNO + 11) \
+ || (r >= FIRST_CCR_REGNO + 16 && r <= FIRST_CCR_REGNO + 31)))
+
static bool
mep_interrupt_saved_reg (int r)
{
if (!mep_interrupt_p ())
return false;
if (r == REGSAVE_CONTROL_TEMP
|| (TARGET_64BIT_CR_REGS && TARGET_COP && r == REGSAVE_CONTROL_TEMP+1))
return true;
if (mep_asm_without_operands_p ()
&& (!fixed_regs[r]
- || (r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO || r == LP_REGNO)))
+ || (r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO || r == LP_REGNO)
+ || IVC2_ISAVED_REG (r)))
return true;
if (!current_function_is_leaf)
/* Function calls mean we need to save $lp. */
- if (r == LP_REGNO)
+ if (r == LP_REGNO || IVC2_ISAVED_REG (r))
return true;
if (!current_function_is_leaf || cfun->machine->doloop_tags > 0)
/* The interrupt handler might use these registers for repeat blocks,
or it might call a function that does so. */
if (r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO)
return true;
if (current_function_is_leaf && call_used_regs[r] && !df_regs_ever_live_p(r))
return false;
/* Functions we call might clobber these. */
if (call_used_regs[r] && !fixed_regs[r])
return true;
/* Additional registers that need to be saved for IVC2. */
- if (TARGET_IVC2
- && (r == FIRST_CCR_REGNO + 1
- || (r >= FIRST_CCR_REGNO + 8 && r <= FIRST_CCR_REGNO + 11)
- || (r >= FIRST_CCR_REGNO + 16 && r <= FIRST_CCR_REGNO + 31)))
+ if (IVC2_ISAVED_REG (r))
return true;
return false;
}
static bool
Index: config/mep/mep-ivc2.cpu
===================================================================
--- config/mep/mep-ivc2.cpu (revision 149360)
+++ config/mep/mep-ivc2.cpu (working copy)
@@ -1460,42 +1460,45 @@
(set croc (c-call DI "ivc2_cpmovfrcc" pc)) )
()
)
; 1111 0000 0000 0111 10000 qqqqq 10000 0 cpmovtocsar0 crqc (c3_1)
(dni cpmovtocsar0_C3 "cpmovtocsar0 $crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar0"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar0") VOLATILE)
"cpmovtocsar0 $crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_csar0 0)
(c-call "ivc2_cpmovtocsar0" pc crqc) )
()
)
; 1111 0000 0000 0111 10000 qqqqq 11111 0 cpmovtocsar1 crqc (c3_1)
(dni cpmovtocsar1_C3 "cpmovtocsar1 $crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar1"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar1") VOLATILE)
"cpmovtocsar1 $crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x1f) (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_csar1 0)
(c-call "ivc2_cpmovtocsar1" pc crqc) )
()
)
; 1111 0000 0000 0111 10000 qqqqq 10001 0 cpmovtocc crqc (c3_1)
(dni cpmovtocc_C3 "cpmovtocc $crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocc"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocc") VOLATILE)
"cpmovtocc $crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpmovtocc" pc crqc) )
()
)
; 1111 000 ooooo 0111 10001 qqqqq 00000 0 cpmov =croc,crqc (c3_1)
(dni cpmov_C3 "cpmov $croc,$crqc C3"
@@ -4945,39 +4948,42 @@
(set crop (c-call DI "ivc2_cpmovfrcc" pc)) )
()
)
; 10001 qqqqq 10000 00000 cpmovtocsar0 crqp (p0_1)
(dni cpmovtocsar0_P0S_P1 "cpmovtocsar0 $crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar0") VOLATILE)
"cpmovtocsar0 $crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_csar0 0)
(c-call "ivc2_cpmovtocsar0" pc crqp) )
()
)
; 10001 qqqqq 11111 00000 cpmovtocsar1 crqp (p0_1)
(dni cpmovtocsar1_P0S_P1 "cpmovtocsar1 $crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar1"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar1") VOLATILE)
"cpmovtocsar1 $crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x1f) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_csar1 0)
(c-call "ivc2_cpmovtocsar1" pc crqp) )
()
)
; 10001 qqqqq 10001 00000 cpmovtocc crqp (p0_1)
(dni cpmovtocc_P0S_P1 "cpmovtocc $crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocc"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocc") VOLATILE)
"cpmovtocc $crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpmovtocc" pc crqp) )
()
)
; 10010 qqqqq ppppp 00000 cpcmpeqz.b crqp,crpp (p0_1)
(dni cpcmpeqz_b_P0S_P1 "cpcmpeqz.b $crqp,$crpp Pn"