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[PATCH] Workaround for Janus 2CC core errata
- From: Daniel Gutson <dgutson at codesourcery dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 01 Jul 2009 03:26:14 -0300
- Subject: [PATCH] Workaround for Janus 2CC core errata
The attached patch implements a work-around for an errata in the Janus 2CC core.
I tested this by running the gcc test suite, including the two new test cases I added in this patch.
If accepted, please commit if for me since I don't have write access.
Thanks,
Daniel.
2009-07-01 Daniel Gutson <dgutson@codesourcery.com>
gcc/
* config/arm/arm.md (*addsi3_carryin_shift): Added "length" clause to handle the extra NOP.
(andsi_not_shiftsi_si): Likewise.
(*thumb1_ashlsi3): Likewise.
(*thumb1_ashrsi3): Likewise.
(*thumb1_lshrsi3): Likewise.
(*thumb1_rotrsi3): Likewise.
(*arm_shiftsi3): Likewise.
(*shiftsi3_compare0): Likewise.
(*shiftsi3_compare0_scratch): Likewise.
(*arm_notsi_shiftsi): Likewise.
(*arm_notsi_shiftsi_compare0): Likewise.
(*arm_not_shiftsi_compare0_scratch): Likewise.
(*arm_cmpsi_shiftsi): Likewise.
(*arm_cmpsi_shiftsi_swp): Likewise.
(*arm_cmpsi_negshiftsi_si): Likewise.
(*arith_shiftsi): Likewise.
(*arith_shiftsi_compare0): Likewise.
(*arith_shiftsi_compare0_scratch): Likewise.
(*sub_shiftsi): Likewise.
(*sub_shiftsi_compare0): Likewise.
(*sub_shiftsi_compare0_scratch): Likewise.
(*if_shift_move): Likewise.
(*if_move_shift): Likewise.
(*if_shift_shift): Likewise.
(*thumb1_ashlsi3_janus2): New. Duplicated pattern to handle the extra NOP.
(*thumb1_ashrsi3_janus2): Likewise.
(*thumb1_lshrsi3_janus2): Likewise.
(*thumb1_rotrsi3_janus2): Likewise.
* config/arm/arm.c (arm_print_operand): Added the nop after the %S pattern.
(arm_override_options): Added handling of the -mfix-janus-2cc flag
* config/arm/arm.h (janus2_code): Declare.
* config/arm/arm.opt (-mfix-janus-2cc): New.
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_arm_no_thumb): New function.
* gcc.target/arm/janus-2cc-shift-1.c: New.
* gcc.target/arm/janus-2cc-shift-2.c: New.
--
Daniel Gutson
CodeSourcery
dgutson@codesourcery.com
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 149128)
+++ gcc/doc/invoke.texi (working copy)
@@ -446,6 +446,7 @@ Objective-C and Objective-C++ Dialects}.
-mfloat-abi=@var{name} -msoft-float -mhard-float -mfpe @gol
-mfp16-format=@var{name}
-mthumb-interwork -mno-thumb-interwork @gol
+-mfix-janus-2cc @gol
-mcpu=@var{name} -march=@var{name} -mfpu=@var{name} @gol
-mstructure-size-boundary=@var{n} @gol
-mabort-on-noreturn @gol
@@ -9450,6 +9451,10 @@ assembler. If you want to force assemble
either add a @samp{.thumb} directive to the source or pass the @option{-mthumb}
option directly to the assembler by prefixing it with @option{-Wa}.
+@item -mfix-janus-2cc
+@opindex mfix-janus-2cc
+Work around hardware errata for Avalent Janus 2CC cores.
+
@item -mtpcs-frame
@opindex mtpcs-frame
Generate a stack frame that is compliant with the Thumb Procedure Call
Index: gcc/testsuite/gcc.target/arm/janus-2cc-shift-2.c
===================================================================
--- gcc/testsuite/gcc.target/arm/janus-2cc-shift-2.c (revision 0)
+++ gcc/testsuite/gcc.target/arm/janus-2cc-shift-2.c (revision 0)
@@ -0,0 +1,17 @@
+/* Check that a nop is inserted after a shift taking a register operand. */
+/* { dg-do compile } */
+/* { dg-options "-mfix-janus-2cc -mthumb" } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+int foo(int x)
+{
+ int y;
+ int z;
+
+ y = x << 4;
+ z = y << x;
+
+ return y+z;
+}
+/* { dg-final { scan-assembler "\tlsl\tr\[0-9], r\[0-9], r\[0-9]\n\tnop\n" } } */
+/* { dg-final { scan-assembler-not "\tlsl\tr\[0-9], r\[0-9], #4\n\tnop\n" } } */
+
Index: gcc/testsuite/gcc.target/arm/janus-2cc-shift-1.c
===================================================================
--- gcc/testsuite/gcc.target/arm/janus-2cc-shift-1.c (revision 0)
+++ gcc/testsuite/gcc.target/arm/janus-2cc-shift-1.c (revision 0)
@@ -0,0 +1,17 @@
+/* Check that a nop is inserted after a shift taking a register operand. */
+/* { dg-do compile } */
+/* { dg-options "-mfix-janus-2cc" } */
+/* { dg-require-effective-target arm_not_thumb } */
+int foo(int x)
+{
+ int y;
+ int z;
+
+ y = x << 4;
+ z = y << x;
+
+ return y+z;
+}
+/* { dg-final { scan-assembler "\tmov\tr\[0-9], r\[0-9], asl r\[0-9]\n\tnop\n" } } */
+/* { dg-final { scan-assembler-not "\tmov\tr\[0-9], r\[0-9], asl #4\n\tnop\n" } } */
+
Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp (revision 149128)
+++ gcc/testsuite/lib/target-supports.exp (working copy)
@@ -1480,6 +1480,15 @@ proc check_effective_target_arm_neon_ok
}
}
+# Return 1 if this is an arm target using 32-bit instructions, but not thumb
+proc check_effective_target_arm_not_thumb { } {
+ return [check_no_compiler_messages arm_not_thumb assembly {
+ #if !defined(__arm__) || defined(__thumb__)
+ #error FOO
+ #endif
+ }]
+}
+
# Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
# used.
Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c (revision 149128)
+++ gcc/config/arm/arm.c (working copy)
@@ -628,6 +628,9 @@ int arm_tune_cortex_a9 = 0;
/* Nonzero if generating Thumb instructions. */
int thumb_code = 0;
+/* Nonzero if generating code for Janus2. */
+int janus2_code = 0;
+
/* Nonzero if we should define __THUMB_INTERWORK__ in the
preprocessor.
XXX This is a bit of a hack, it's intended to help work around
@@ -1529,6 +1532,9 @@ arm_override_options (void)
arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
thumb_code = (TARGET_ARM == 0);
+ janus2_code = (TARGET_FIX_JANUS != 0);
+ if (janus2_code && TARGET_THUMB2)
+ error ("janus2 fix is not applicable when targeting a thumb2 core");
arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
@@ -13694,7 +13700,11 @@ arm_print_operand (FILE *stream, rtx x,
{
fprintf (stream, ", %s ", shift);
if (val == -1)
- arm_print_operand (stream, XEXP (x, 1), 0);
+ {
+ arm_print_operand (stream, XEXP (x, 1), 0);
+ if (janus2_code)
+ fprintf(stream, "\n\tnop");
+ }
else
fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
}
Index: gcc/config/arm/arm.h
===================================================================
--- gcc/config/arm/arm.h (revision 149128)
+++ gcc/config/arm/arm.h (working copy)
@@ -407,6 +407,9 @@ extern int arm_ld_sched;
/* Nonzero if generating thumb code. */
extern int thumb_code;
+/* Nonzero if generating Janus2 code. */
+extern int janus2_code;
+
/* Nonzero if this chip is a StrongARM. */
extern int arm_tune_strongarm;
Index: gcc/config/arm/arm.opt
===================================================================
--- gcc/config/arm/arm.opt (revision 149128)
+++ gcc/config/arm/arm.opt (working copy)
@@ -97,6 +97,10 @@ mhard-float
Target RejectNegative
Alias for -mfloat-abi=hard
+mfix-janus-2cc
+Target Report Mask(FIX_JANUS)
+Work around hardware errata for Avalent Janus 2CC cores.
+
mlittle-endian
Target Report RejectNegative InverseMask(BIG_END)
Assume target CPU is configured as little endian
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md (revision 149128)
+++ gcc/config/arm/arm.md (working copy)
@@ -145,6 +145,10 @@ (define_constants
; patterns that share the same RTL in both ARM and Thumb code.
(define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code")))
+; FIX_JANUS is set to 'yes' when compiling for Janus2, it causes to
+; add a nop after shifts, in order to work around a Janus2 bug
+(define_attr "fix_janus" "no,yes" (const (symbol_ref "janus2_code")))
+
; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects
; scheduling decisions for the load unit and the multiplier.
(define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_tune_strongarm")))
@@ -870,7 +874,11 @@ (define_insn "*addsi3_carryin_shift"
[(set_attr "conds" "use")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*addsi3_carryin_alt1"
@@ -2544,7 +2552,11 @@ (define_insn "andsi_not_shiftsi_si"
(set_attr "shift" "2")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*andsi_notsi_si_compare0"
@@ -3179,11 +3191,23 @@ (define_insn "*thumb1_ashlsi3"
[(set (match_operand:SI 0 "register_operand" "=l,l")
(ashift:SI (match_operand:SI 1 "register_operand" "l,0")
(match_operand:SI 2 "nonmemory_operand" "N,l")))]
- "TARGET_THUMB1"
+ "TARGET_THUMB1 && !janus2_code"
"lsl\\t%0, %1, %2"
[(set_attr "length" "2")]
)
+(define_insn "*thumb1_ashlsi3_janus2"
+ [(set (match_operand:SI 0 "register_operand" "=l,l")
+ (ashift:SI (match_operand:SI 1 "register_operand" "l,0")
+ (match_operand:SI 2 "nonmemory_operand" "N,l")))]
+ "TARGET_THUMB1 && janus2_code"
+ "@
+ lsl\\t%0, %1, %2
+ lsl\\t%0, %1, %2\;nop"
+ [(set_attr "length" "2,4")]
+)
+
+
(define_expand "ashrdi3"
[(set (match_operand:DI 0 "s_register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "s_register_operand" "")
@@ -3235,11 +3259,22 @@ (define_insn "*thumb1_ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=l,l")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
(match_operand:SI 2 "nonmemory_operand" "N,l")))]
- "TARGET_THUMB1"
+ "TARGET_THUMB1 && !janus2_code"
"asr\\t%0, %1, %2"
[(set_attr "length" "2")]
)
+(define_insn "*thumb1_ashrsi3_janus2"
+ [(set (match_operand:SI 0 "register_operand" "=l,l")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
+ (match_operand:SI 2 "nonmemory_operand" "N,l")))]
+ "TARGET_THUMB1 && janus2_code"
+ "@
+ asr\\t%0, %1, %2
+ asr\\t%0, %1, %2\;nop"
+ [(set_attr "length" "2,4")]
+)
+
(define_expand "lshrdi3"
[(set (match_operand:DI 0 "s_register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "s_register_operand" "")
@@ -3294,11 +3329,22 @@ (define_insn "*thumb1_lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=l,l")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
(match_operand:SI 2 "nonmemory_operand" "N,l")))]
- "TARGET_THUMB1"
+ "TARGET_THUMB1 && !janus2_code"
"lsr\\t%0, %1, %2"
[(set_attr "length" "2")]
)
+(define_insn "*thumb1_lshrsi3_janus2"
+ [(set (match_operand:SI 0 "register_operand" "=l,l")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
+ (match_operand:SI 2 "nonmemory_operand" "N,l")))]
+ "TARGET_THUMB1 && janus2_code"
+ "@
+ lsr\\t%0, %1, %2
+ lsr\\t%0, %1, %2; nop"
+ [(set_attr "length" "2,4")]
+)
+
(define_expand "rotlsi3"
[(set (match_operand:SI 0 "s_register_operand" "")
(rotatert:SI (match_operand:SI 1 "s_register_operand" "")
@@ -3340,11 +3386,20 @@ (define_insn "*thumb1_rotrsi3"
[(set (match_operand:SI 0 "register_operand" "=l")
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "register_operand" "l")))]
- "TARGET_THUMB1"
+ "TARGET_THUMB1 && !janus2_code"
"ror\\t%0, %0, %2"
[(set_attr "length" "2")]
)
+(define_insn "*thumb1_rotrsi3_janus2"
+ [(set (match_operand:SI 0 "register_operand" "=l")
+ (rotatert:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "register_operand" "l")))]
+ "TARGET_THUMB1 && janus2_code"
+ "ror\\t%0, %0, %2; nop"
+ [(set_attr "length" "4")]
+)
+
(define_insn "*arm_shiftsi3"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(match_operator:SI 3 "shift_operator"
@@ -3356,7 +3411,11 @@ (define_insn "*arm_shiftsi3"
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*shiftsi3_compare0"
@@ -3373,7 +3432,11 @@ (define_insn "*shiftsi3_compare0"
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*shiftsi3_compare0_scratch"
@@ -3386,7 +3449,11 @@ (define_insn "*shiftsi3_compare0_scratch
"TARGET_32BIT"
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
- (set_attr "shift" "1")]
+ (set_attr "shift" "1")
+ (set (attr "length") (if_then_else (and (match_operand 2 "s_register_operand" "")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*arm_notsi_shiftsi"
@@ -3400,7 +3467,11 @@ (define_insn "*arm_notsi_shiftsi"
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*arm_notsi_shiftsi_compare0"
@@ -3417,7 +3488,11 @@ (define_insn "*arm_notsi_shiftsi_compare
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*arm_not_shiftsi_compare0_scratch"
@@ -3433,7 +3508,11 @@ (define_insn "*arm_not_shiftsi_compare0_
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
;; We don't really have extzv, but defining this using shifts helps
@@ -7710,7 +7789,11 @@ (define_insn "*arm_cmpsi_shiftsi"
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*arm_cmpsi_shiftsi_swp"
@@ -7725,7 +7808,11 @@ (define_insn "*arm_cmpsi_shiftsi_swp"
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*arm_cmpsi_negshiftsi_si"
@@ -7740,7 +7827,11 @@ (define_insn "*arm_cmpsi_negshiftsi_si"
[(set_attr "conds" "set")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
;; Cirrus SF compare instruction
@@ -8992,7 +9083,11 @@ (define_insn "*arith_shiftsi"
(set_attr "shift" "4")
(set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_split
@@ -9030,7 +9125,11 @@ (define_insn "*arith_shiftsi_compare0"
(set_attr "shift" "4")
(set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*arith_shiftsi_compare0_scratch"
@@ -9048,7 +9147,11 @@ (define_insn "*arith_shiftsi_compare0_sc
(set_attr "shift" "4")
(set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*sub_shiftsi"
@@ -9063,7 +9166,11 @@ (define_insn "*sub_shiftsi"
(set_attr "shift" "3")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*sub_shiftsi_compare0"
@@ -9083,7 +9190,11 @@ (define_insn "*sub_shiftsi_compare0"
(set_attr "shift" "3")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
(define_insn "*sub_shiftsi_compare0_scratch"
@@ -9101,7 +9212,11 @@ (define_insn "*sub_shiftsi_compare0_scra
(set_attr "shift" "3")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4)))]
)
@@ -9975,10 +10090,22 @@ (define_insn "*if_shift_move"
mvn%D5\\t%0, #%B1\;mov%d5\\t%0, %2%S4"
[(set_attr "conds" "use")
(set_attr "shift" "2")
- (set_attr "length" "4,8,8")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set_attr_alternative "length"
+ [(if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4))
+ (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 12)
+ (const_int 8))
+ (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 12)
+ (const_int 8))])]
)
(define_insn "*ifcompare_move_shift"
@@ -10014,10 +10141,23 @@ (define_insn "*if_move_shift"
mvn%d5\\t%0, #%B1\;mov%D5\\t%0, %2%S4"
[(set_attr "conds" "use")
(set_attr "shift" "2")
- (set_attr "length" "4,8,8")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set_attr_alternative "length"
+ [(if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 8)
+ (const_int 4))
+ (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 12)
+ (const_int 8))
+ (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 12)
+ (const_int 8))])
+ (set_attr "insn" "mov")]
)
(define_insn "*ifcompare_shift_shift"
@@ -10054,12 +10194,15 @@ (define_insn "*if_shift_shift"
"mov%d5\\t%0, %1%S6\;mov%D5\\t%0, %3%S7"
[(set_attr "conds" "use")
(set_attr "shift" "1")
- (set_attr "length" "8")
(set (attr "type") (if_then_else
(and (match_operand 2 "const_int_operand" "")
(match_operand 4 "const_int_operand" ""))
(const_string "alu_shift")
- (const_string "alu_shift_reg")))]
+ (const_string "alu_shift_reg")))
+ (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
+ (eq_attr "fix_janus" "yes"))
+ (const_int 16)
+ (const_int 8)))]
)
(define_insn "*ifcompare_not_arith"