This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: PATCH: PR target/40470: unable to find a registe r to spill in class ‘SSE_FIRST_REG’


On Thu, Jun 18, 2009 at 10:49 AM, Jeff Law<law@redhat.com> wrote:

>
> The whole point of copying xmm0 to p666 is to free xmm0 ?so that it can be
> used by other insns.
>
> Combine's removal of p666 = xmm0 is wrong as is changing the last insn above
> to use xmm0 instead of p666.
>
>

cant_combine_insn_p has

  if (REG_P (src) && REG_P (dest)
      && ((REGNO (src) < FIRST_PSEUDO_REGISTER
           && ! fixed_regs[REGNO (src)]
           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
          || (REGNO (dest) < FIRST_PSEUDO_REGISTER
              && ! fixed_regs[REGNO (dest)]
              && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
    return 1;

When I add SSE_FIRST_REG/xmm0 to CLASS_LIKELY_SPILLED_P,
all testcases compile. However, xmm0 is used for FP return for
x86-64, I don't know the performance impact of this change.
xmm0 is a fixed register only for a handful SSE4 insns, which
can only be generated from intrinsics. Should we really go down
this route?

-- 
H.J.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]