This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[PATCH ARM] Fix PR 10242
- From: Richard Earnshaw <Richard dot Earnshaw at buzzard dot freeserve dot co dot uk>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Thu, 04 Jun 2009 00:34:00 +0100
- Subject: [PATCH ARM] Fix PR 10242
If we have an add of a constant to an eliminable register, then it is
not a particularly good idea to split the constant into a sequence of
add-immediate instructions until we know what the final adjustment will
be; since otherwise we end up with a longer sequence of adds that
necessary. Once we know the final adjustment we can generate the
optimal sequence directly.
2009-06-04 Richard Earnshaw <rearnsha@arm.com>
PR target/10242
* arm.md (arm_addsi3): Don't try to split an add with an
eliminable register until after reload has completed.
*** arm.md (revision 144914)
--- arm.md (local)
*************** (define_insn_and_split "*arm_addsi3"
*** 620,629 ****
sub%?\\t%0, %1, #%n2
sub%?\\t%0, %1, #%n2
#"
! "TARGET_32BIT &&
! GET_CODE (operands[2]) == CONST_INT
&& !(const_ok_for_arm (INTVAL (operands[2]))
! || const_ok_for_arm (-INTVAL (operands[2])))"
[(clobber (const_int 0))]
"
arm_split_constant (PLUS, SImode, curr_insn,
--- 620,630 ----
sub%?\\t%0, %1, #%n2
sub%?\\t%0, %1, #%n2
#"
! "TARGET_32BIT
! && GET_CODE (operands[2]) == CONST_INT
&& !(const_ok_for_arm (INTVAL (operands[2]))
! || const_ok_for_arm (-INTVAL (operands[2])))
! && (reload_completed || !arm_eliminable_register (operands[1]))"
[(clobber (const_int 0))]
"
arm_split_constant (PLUS, SImode, curr_insn,