[PATCH, ARM] Add split patterns for thumb_zero_extendXXdi

[Richard Earnshaw <Richard dot Earnshaw at buzzard dot freeserve dot co dot uk>]

This patch adds some simple split patterns for the thumb2 zero_extend:DI
instructions.  It results in slightly better code with more scheduling
freedom and the ability to exploit 16-bit instructions via existing
optimizations.

Now we have the split patterns, I'm no-longer worried about emitting
some redundant moves that might potentially confuse the
conditional-execution counter; the patterns will only not split at -O0.

R.

2009-05-29  Richard Earnshaw  <rearnsha@arm.com>

	* config/arm/thumb2.md (thumb2_zero_extendsidi2): Add a split
	component.
	(thumb2_zero_extendqidi2): Likewise.

*** config/arm/thumb2.md	(revision 147998)
--- config/arm/thumb2.md	(local)
*************** (define_insn "*thumb2_movcond"
*** 849,878 ****
  
  ;; Zero and sign extension instructions.
  
! (define_insn "*thumb2_zero_extendsidi2"
    [(set (match_operand:DI 0 "s_register_operand" "=r")
          (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
    "TARGET_THUMB2"
!   "*
!     /* ??? Output both instructions unconditionally, otherwise the conditional
!        execution insn counter gets confused.
!     if (REGNO (operands[1])
!         != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) */
!       output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
!     return \"mov%?\\t%R0, #0\";
    "
    [(set_attr "length" "8")
     (set_attr "ce_count" "2")
     (set_attr "predicable" "yes")]
  )
  
! (define_insn "*thumb2_zero_extendqidi2"
    [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
  	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
    "TARGET_THUMB2"
    "@
!    and%?\\t%Q0, %1, #255\;mov%?\\t%R0, #0
     ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
    [(set_attr "length" "8")
     (set_attr "ce_count" "2")
     (set_attr "predicable" "yes")
--- 849,892 ----
  
  ;; Zero and sign extension instructions.
  
! (define_insn_and_split "*thumb2_zero_extendsidi2"
    [(set (match_operand:DI 0 "s_register_operand" "=r")
          (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
    "TARGET_THUMB2"
!   "mov%?\\t%Q0, %1\;mov%?\\t%R0, #0"
!   "&& reload_completed"
!   [(set (match_dup 0) (match_dup 1))]
!   "
!   {
!     rtx lo_part = gen_lowpart (SImode, operands[0]);
!     if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
!       emit_move_insn (lo_part, operands[1]);
!     operands[0] = gen_highpart (SImode, operands[0]);
!     operands[1] = const0_rtx;
!   }
    "
    [(set_attr "length" "8")
     (set_attr "ce_count" "2")
     (set_attr "predicable" "yes")]
  )
  
! (define_insn_and_split "*thumb2_zero_extendqidi2"
    [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
  	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
    "TARGET_THUMB2"
    "@
!    uxtb%?\\t%Q0, %1\;mov%?\\t%R0, #0
     ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
+   "&& reload_completed"
+   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
+    (set (match_dup 2) (match_dup 3))]
+   "
+   {
+     operands[2] = gen_highpart (SImode, operands[0]);
+     operands[0] = gen_lowpart (SImode, operands[0]);
+     operands[3] = const0_rtx;
+   }
+   "
    [(set_attr "length" "8")
     (set_attr "ce_count" "2")
     (set_attr "predicable" "yes")