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Re: [PATCH 1/3] cond-optab merge target-independent bits
> Nice cleanup indeed! There is a glitch though: all the ZERO_EXTRACT tests are
> applied to the wrong operand in the new patterns.
Done.
> The patterns seqdi_special & snedi_special will be unused too so I think you
> should delete them and rename seqdi_special_trunc & gen_snedi_special_trunc.
Done.
> Do we still need the associated splitters seqdi_zero, neg_seqdi_zero,
> snedi_zero, neg_snedi_zero, seqsi_zero_extend and snesi_zero_extend?
Probably not, I can remove them but I'll do this further testing after
the merge.
> Nothing else glaring apart from the missing comments for new parameters in
> gen_compare_reg_1, gen_compare_reg and gen_v9_scc.
Done.
Paolo
sparc fixes
2009-04-28 Paolo Bonzini <bonzini@gnu.org>
* config/sparc/sparc.c (gen_compare_reg_1): Fix comment.
(gen_compare_reg): Add comment.
(emit_scc_insn): Fix comment. Adjust for renamed seqdi_special_trunc
and snedi_special_trunc patterns.
* config/sparc/sparc.md (cbranch*, cstore*): Fix ZERO_EXTRACT
operand numbers.
(seqdi_special, snedi_special): Use expansion of seqdi_special_trunc
and snedi_special_trunc.
(seqdi_special_trunc, snedi_special_trunc): Delete.
Index: gcc/config/sparc/sparc.c
===================================================================
--- gcc/config/sparc/sparc.c (branch cond-optab)
+++ gcc/config/sparc/sparc.c (working copy)
@@ -1997,7 +1997,8 @@ select_cc_mode (enum rtx_code op, rtx x,
}
}
-/* Emit the compare insn and return the CC reg for a CODE comparison. */
+/* Emit the compare insn and return the CC reg for a CODE comparison
+ with operands X and Y. */
static rtx
gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y)
@@ -2063,6 +2064,9 @@ gen_compare_reg_1 (enum rtx_code code, r
return cc_reg;
}
+
+/* Emit the compare insn and return the CC reg for the comparison in CMP. */
+
rtx
gen_compare_reg (rtx cmp)
{
@@ -2070,10 +2074,9 @@ gen_compare_reg (rtx cmp)
}
/* This function is used for v9 only.
- CODE is the code for an Scc's comparison.
DEST is the target of the Scc insn.
- X is the value we compare against const0_rtx (which hasn't
- been generated yet).
+ CODE is the code for an Scc's comparison.
+ X and Y are the values we compare.
This function is needed to turn
@@ -2204,7 +2207,7 @@ emit_scc_insn (rtx operands[])
}
else if (GET_MODE (x) == DImode)
{
- rtx pat = gen_seqdi_special_trunc (operands[0], x, y);
+ rtx pat = gen_seqdi_special (operands[0], x, y);
emit_insn (pat);
return true;
}
@@ -2220,7 +2223,7 @@ emit_scc_insn (rtx operands[])
}
else if (GET_MODE (x) == DImode)
{
- rtx pat = gen_snedi_special_trunc (operands[0], x, y);
+ rtx pat = gen_snedi_special (operands[0], x, y);
emit_insn (pat);
return true;
}
@@ -2234,9 +2237,9 @@ emit_scc_insn (rtx operands[])
return true;
}
- /* We can do LTU and GEU using the addx/subx instructions too. And
- for GTU/LEU, if both operands are registers swap them and fall
- back to the easy case. */
+ /* We can do LTU and GEU using the addx/subx instructions too. And
+ for GTU/LEU, if both operands are registers swap them and fall
+ back to the easy case. */
if (code == GTU || code == LEU)
{
if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
Index: gcc/config/sparc/sparc.md
===================================================================
--- gcc/config/sparc/sparc.md (branch cond-optab)
+++ gcc/config/sparc/sparc.md (working copy)
@@ -447,8 +447,8 @@
(clobber (match_operand:SI 0 "register_operand"))]
""
{
- if (GET_CODE (operands[1]) == ZERO_EXTRACT && operands[2] != const0_rtx)
- operands[1] = force_reg (SImode, operands[1]);
+ if (GET_CODE (operands[2]) == ZERO_EXTRACT && operands[3] != const0_rtx)
+ operands[2] = force_reg (SImode, operands[2]);
if (emit_scc_insn (operands)) DONE; else FAIL;
})
@@ -459,8 +459,8 @@
(clobber (match_operand:SI 0 "register_operand"))]
"TARGET_ARCH64"
{
- if (GET_CODE (operands[1]) == ZERO_EXTRACT && operands[2] != const0_rtx)
- operands[1] = force_reg (DImode, operands[1]);
+ if (GET_CODE (operands[2]) == ZERO_EXTRACT && operands[3] != const0_rtx)
+ operands[2] = force_reg (DImode, operands[2]);
if (emit_scc_insn (operands)) DONE; else FAIL;
})
@@ -491,8 +491,8 @@
[(set (match_dup 3)
(xor:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")))
- (set (match_operand:DI 0 "register_operand" "")
- (eq:DI (match_dup 3) (const_int 0)))]
+ (set (match_operand:SI 0 "register_operand" "")
+ (eq:SI (match_dup 3) (const_int 0)))]
"TARGET_ARCH64"
{ operands[3] = gen_reg_rtx (DImode); })
@@ -510,24 +510,6 @@
[(set (match_dup 3)
(xor:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")))
- (set (match_operand:DI 0 "register_operand" "")
- (ne:DI (match_dup 3) (const_int 0)))]
- "TARGET_ARCH64"
- { operands[3] = gen_reg_rtx (DImode); })
-
-(define_expand "seqdi_special_trunc"
- [(set (match_dup 3)
- (xor:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
- (set (match_operand:SI 0 "register_operand" "")
- (eq:SI (match_dup 3) (const_int 0)))]
- "TARGET_ARCH64"
- { operands[3] = gen_reg_rtx (DImode); })
-
-(define_expand "snedi_special_trunc"
- [(set (match_dup 3)
- (xor:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
(set (match_operand:SI 0 "register_operand" "")
(ne:SI (match_dup 3) (const_int 0)))]
"TARGET_ARCH64"
@@ -941,8 +923,8 @@
(use (match_operand 3 ""))]
""
{
- if (GET_CODE (operands[0]) == ZERO_EXTRACT && operands[1] != const0_rtx)
- operands[0] = force_reg (SImode, operands[0]);
+ if (GET_CODE (operands[1]) == ZERO_EXTRACT && operands[2] != const0_rtx)
+ operands[1] = force_reg (SImode, operands[1]);
emit_conditional_branch_insn (operands);
DONE;
})
@@ -954,8 +936,8 @@
(use (match_operand 3 ""))]
"TARGET_ARCH64"
{
- if (GET_CODE (operands[0]) == ZERO_EXTRACT && operands[1] != const0_rtx)
- operands[0] = force_reg (DImode, operands[0]);
+ if (GET_CODE (operands[1]) == ZERO_EXTRACT && operands[2] != const0_rtx)
+ operands[1] = force_reg (DImode, operands[1]);
emit_conditional_branch_insn (operands);
DONE;
})