Re: RFA: patch modifying ColdFire, power4, an power5 pipeline descriptions

[Pat Haugen <pthaugen at us dot ibm dot com>]

> Index: gcc/config/rs6000/power5.md
> ===================================================================
> --- gcc/config/rs6000/power5.md   (revision 145316)
> +++ gcc/config/rs6000/power5.md   (working copy)
> @@ -40,16 +40,12 @@
>            |(du4_power5,lsu1_power5)")
>
>  (define_reservation "iq_power5"
> -          "(du1_power5,iu1_power5)\
> -          |(du2_power5,iu2_power5)\
> -          |(du3_power5,iu2_power5)\
> -          |(du4_power5,iu1_power5)")
> +          "(du1_power5|du2_power5|du3_power5|du4_power5),\
> +                     (iu1_power5|iu2_power5)")
>
>  (define_reservation "fpq_power5"
> -          "(du1_power5,fpu1_power5)\
> -          |(du2_power5,fpu2_power5)\
> -          |(du3_power5,fpu2_power5)\
> -          |(du4_power5,fpu1_power5)")
> +          "(du1_power5|du2_power5|du3_power5|du4_power5),\
> +                     (fpu1_power5|fpu2_power5)")
>

Not sure I fully understand the problem you're attempting to solve, but
based on the examples above which are repeated throughout the
power4/power5 .md files, it looks like this would now ignore the dispatch
slot to issue queue affinity that is present in the processors. Assuming we
have 2 fixed point (FX) and 2 floating point (FP) insns to schedule, the
order FX,FP,FX,FP or FX,FX,FP,FP (and swapped permutations) will result in
4 insns dispatched with one of each type going to the two (of each) FX/FP
issue queues (and hence executing all 4 insns at the same time, one on each
of the 2 FX/FP execution units).  With your change it looks like an order
of FX,FP,FP,FX (or FP,FX,FX,FP) is not restricted, in which case there
would be 4 insns dispatched but both FX would go to the same FX issue queue
and likewise both FP would go to the same FP issue queue, meaning we're
only issuing 2 insns at a time (1 FX and 1 FP).

-Pat