[cond-optab] Convert frv

[Paolo Bonzini <bonzini at gnu dot org>]

FRV is rather complex for an embedded target, but didn't pose
any problem.

Paolo

        * config/frv/frv.md (cbranchsi4, cbranchsf4, cbranchdf4,
	cstoresi4, cstoresf4, cstoredf4): New.
        (cmpdi, cmpsi, cmpsf, cmpdf, bCC, sCC): Remove.
        * config/frv/frv-protos.h (frv_emit_cbranch, frv_emit_scc):
        Receive the entire operands array.
        * config/frv/frv.h (frv_compare_op0,
        frv_compare_op1): Delete.
        * config/frv/frv.c (frv_compare_op0,
        frv_compare_op1): Delete.
        * config/frv/frv-protos.h (frv_emit_cbranch, frv_emit_scc):
        Get test/op0/op1 from the operands array.
        (frv_emit_cond_move): Get test/op0/op1 from the test_rtx.

Index: gcc/config/frv/frv.h
===================================================================
--- gcc/config/frv/frv.h	(branch cond-optab)
+++ gcc/config/frv/frv.h	(working copy)
@@ -2936,9 +2936,6 @@ enum frv_builtins
 /* Enable prototypes on the call rtl functions.  */
 #define MD_CALL_PROTOTYPES 1
 
-extern GTY(()) rtx frv_compare_op0;			/* operand save for */
-extern GTY(()) rtx frv_compare_op1;			/* comparison generation */
-
 #define CPU_UNITS_QUERY 1
 
 #ifdef __FRV_FDPIC__
Index: gcc/config/frv/frv.md
===================================================================
--- gcc/config/frv/frv.md	(branch cond-optab)
+++ gcc/config/frv/frv.md	(working copy)
@@ -3734,59 +3734,7 @@
 ;; ::
 ;; ::::::::::::::::::::
 
-;; Note, we store the operands in the comparison insns, and use them later
-;; when generating the branch or scc operation.
-
-;; First the routines called by the machine independent part of the compiler
-(define_expand "cmpsi"
-  [(set (cc0)
-        (compare (match_operand:SI 0 "integer_register_operand" "")
-  		 (match_operand:SI 1 "gpr_or_int10_operand" "")))]
-  ""
-  "
-{
-  frv_compare_op0 = operands[0];
-  frv_compare_op1 = operands[1];
-  DONE;
-}")
-
-;(define_expand "cmpdi"
-;  [(set (cc0)
-;        (compare (match_operand:DI 0 "register_operand" "")
-;  		 (match_operand:DI 1 "nonmemory_operand" "")))]
-;  ""
-;  "
-;{
-;  frv_compare_op0 = operands[0];
-;  frv_compare_op1 = operands[1];
-;  DONE;
-;}")
-
-(define_expand "cmpsf"
- [(set (cc0)
-       (compare (match_operand:SF 0 "fpr_operand" "")
- 		 (match_operand:SF 1 "fpr_operand" "")))]
- "TARGET_HARD_FLOAT"
- "
-{
-  frv_compare_op0 = operands[0];
-  frv_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmpdf"
-  [(set (cc0)
-        (compare (match_operand:DF 0 "fpr_operand" "")
-  		 (match_operand:DF 1 "fpr_operand" "")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
-  "
-{
-  frv_compare_op0 = operands[0];
-  frv_compare_op1 = operands[1];
-  DONE;
-}")
-
-;; Now, the actual comparisons, generated by the branch and/or scc operations
+;; The comparisons are generated by the branch and/or scc operations
 
 (define_insn "cmpsi_cc"
   [(set (match_operand:CC 0 "icc_operand" "=t,t")
@@ -3847,137 +3795,31 @@
 ;; ::::::::::::::::::::
 
 ;; Define_expands called by the machine independent part of the compiler
-;; to allocate a new comparison register.  Each of these named patterns
-;; must be present, and they cannot be amalgamated into one pattern.
-;;
-;; If a fixed condition code register is being used, (as opposed to, say,
-;; using cc0), then the expands should look like this:
-;;
-;; (define_expand "<name_of_test>"
-;;   [(set (reg:CC <number_of_CC_register>)
-;; 	(compare:CC (match_dup 1)
-;; 		    (match_dup 2)))
-;;    (set (pc)
-;; 	(if_then_else (eq:CC (reg:CC <number_of_CC_register>)
-;; 			     (const_int 0))
-;; 		      (label_ref (match_operand 0 "" ""))
-;; 		      (pc)))]
-;;   ""
-;;   "{
-;;     operands[1] = frv_compare_op0;
-;;     operands[2] = frv_compare_op1;
-;;   }"
-;; )
-
-(define_expand "beq"
-  [(use (match_operand 0 "" ""))]
-  ""
-  "
-{
-  if (! frv_emit_cond_branch (EQ, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "bne"
-  [(use (match_operand 0 "" ""))]
-  ""
-  "
-{
-  if (! frv_emit_cond_branch (NE, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "blt"
-  [(use (match_operand 0 "" ""))]
-  ""
-  "
-{
-  if (! frv_emit_cond_branch (LT, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "ble"
-  [(use (match_operand 0 "" ""))]
-  ""
-  "
-{
-  if (! frv_emit_cond_branch (LE, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "bgt"
-  [(use (match_operand 0 "" ""))]
-  ""
-  "
-{
-  if (! frv_emit_cond_branch (GT, operands[0]))
-    FAIL;
+;; to allocate a new comparison register.
 
-  DONE;
-}")
-
-(define_expand "bge"
-  [(use (match_operand 0 "" ""))]
-  ""
-  "
-{
-  if (! frv_emit_cond_branch (GE, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "bltu"
-  [(use (match_operand 0 "" ""))]
-  ""
-  "
-{
-  if (! frv_emit_cond_branch (LTU, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "bleu"
-  [(use (match_operand 0 "" ""))]
-  ""
-  "
-{
-  if (! frv_emit_cond_branch (LEU, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "bgtu"
-  [(use (match_operand 0 "" ""))]
-  ""
-  "
-{
-  if (! frv_emit_cond_branch (GTU, operands[0]))
-    FAIL;
+(define_expand "cbranchdf4"
+  [(use (match_operator 0 "ordered_comparison_operator"
+         [(match_operand:DF 1 "fpr_operand" "")
+          (match_operand:DF 2 "fpr_operand" "")]))
+   (use (match_operand 3 ""))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
+  { if (frv_emit_cond_branch (operands)) DONE; else FAIL; })
 
-  DONE;
-}")
+(define_expand "cbranchsf4"
+  [(use (match_operator 0 "ordered_comparison_operator"
+         [(match_operand:SF 1 "fpr_operand" "")
+          (match_operand:SF 2 "fpr_operand" "")]))
+   (use (match_operand 3 ""))]
+  "TARGET_HARD_FLOAT"
+  { if (frv_emit_cond_branch (operands)) DONE; else FAIL; })
 
-(define_expand "bgeu"
-  [(use (match_operand 0 "" ""))]
+(define_expand "cbranchsi4"
+  [(use (match_operator 0 "ordered_comparison_operator"
+         [(match_operand:SI 1 "integer_register_operand" "")
+          (match_operand:SI 2 "gpr_or_int10_operand" "")]))
+   (use (match_operand 3 ""))]
   ""
-  "
-{
-  if (! frv_emit_cond_branch (GEU, operands[0]))
-    FAIL;
-
-  DONE;
-}")
+  { if (frv_emit_cond_branch (operands)) DONE; else FAIL; })
 
 ;; Actual branches.  We must allow for the (label_ref) and the (pc) to be
 ;; swapped.  If they are swapped, it reverses the sense of the branch.
@@ -4142,115 +3984,29 @@
 ;; Define_expands called by the machine independent part of the compiler
 ;; to allocate a new comparison register
 
-(define_expand "seq"
-  [(match_operand:SI 0 "integer_register_operand" "")]
-  "TARGET_SCC"
-  "
-{
-  if (! frv_emit_scc (EQ, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "sne"
-  [(match_operand:SI 0 "integer_register_operand" "")]
-  "TARGET_SCC"
-  "
-{
-  if (! frv_emit_scc (NE, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "slt"
-  [(match_operand:SI 0 "integer_register_operand" "")]
-  "TARGET_SCC"
-  "
-{
-  if (! frv_emit_scc (LT, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "sle"
-  [(match_operand:SI 0 "integer_register_operand" "")]
-  "TARGET_SCC"
-  "
-{
-  if (! frv_emit_scc (LE, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "sgt"
-  [(match_operand:SI 0 "integer_register_operand" "")]
-  "TARGET_SCC"
-  "
-{
-  if (! frv_emit_scc (GT, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "sge"
-  [(match_operand:SI 0 "integer_register_operand" "")]
-  "TARGET_SCC"
-  "
-{
-  if (! frv_emit_scc (GE, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "sltu"
-  [(match_operand:SI 0 "integer_register_operand" "")]
-  "TARGET_SCC"
-  "
-{
-  if (! frv_emit_scc (LTU, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "sleu"
-  [(match_operand:SI 0 "integer_register_operand" "")]
-  "TARGET_SCC"
-  "
-{
-  if (! frv_emit_scc (LEU, operands[0]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "sgtu"
-  [(match_operand:SI 0 "integer_register_operand" "")]
-  "TARGET_SCC"
-  "
-{
-  if (! frv_emit_scc (GTU, operands[0]))
-    FAIL;
-
-  DONE;
-}")
+(define_expand "cstoredf4"
+  [(use (match_operator:SI 1 "ordered_comparison_operator"
+         [(match_operand:DF 2 "fpr_operand")
+          (match_operand:DF 3 "fpr_operand")]))
+   (clobber (match_operand:SI 0 "register_operand"))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE"
+  { if (frv_emit_scc (operands)) DONE; else FAIL; })
 
-(define_expand "sgeu"
-  [(match_operand:SI 0 "integer_register_operand" "")]
-  "TARGET_SCC"
-  "
-{
-  if (! frv_emit_scc (GEU, operands[0]))
-    FAIL;
+(define_expand "cstoresf4"
+  [(use (match_operator:SI 1 "ordered_comparison_operator"
+         [(match_operand:SF 2 "fpr_operand")
+          (match_operand:SF 3 "fpr_operand")]))
+   (clobber (match_operand:SI 0 "register_operand"))]
+  "TARGET_HARD_FLOAT"
+  { if (frv_emit_scc (operands)) DONE; else FAIL; })
 
-  DONE;
-}")
+(define_expand "cstoresi4"
+  [(use (match_operator:SI 1 "ordered_comparison_operator"
+         [(match_operand:SI 2 "integer_register_operand")
+          (match_operand:SI 3 "gpr_or_int10_operand")]))
+   (clobber (match_operand:SI 0 "register_operand"))]
+  ""
+  { if (frv_emit_scc (operands)) DONE; else FAIL; })
 
 (define_insn "*scc_int"
   [(set (match_operand:SI 0 "integer_register_operand" "=d")
Index: gcc/config/frv/frv-protos.h
===================================================================
--- gcc/config/frv/frv-protos.h	(branch cond-optab)
+++ gcc/config/frv/frv-protos.h	(working copy)
@@ -82,8 +82,8 @@ extern const char *output_move_single	(r
 extern const char *output_move_double	(rtx *, rtx);
 extern const char *output_condmove_single
 					(rtx *, rtx);
-extern int frv_emit_cond_branch		(enum rtx_code, rtx);
-extern int frv_emit_scc			(enum rtx_code, rtx);
+extern int frv_emit_cond_branch		(rtx *);
+extern int frv_emit_scc			(rtx *);
 extern rtx frv_split_scc		(rtx, rtx, rtx, rtx, HOST_WIDE_INT);
 extern int frv_emit_cond_move		(rtx, rtx, rtx, rtx);
 extern rtx frv_split_cond_move		(rtx *);
Index: gcc/config/frv/frv.c
===================================================================
--- gcc/config/frv/frv.c	(branch cond-optab)
+++ gcc/config/frv/frv.c	(working copy)
@@ -193,11 +193,6 @@ typedef struct
   int base_offset;
 } frv_frame_accessor_t;
 
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  */
-rtx frv_compare_op0;
-rtx frv_compare_op1;
-
 /* Conditional execution support gathered together in one structure.  */
 typedef struct
   {
@@ -4731,19 +4726,18 @@ frv_emit_comparison (enum rtx_code test,
 }
 
 
-/* Emit code for a conditional branch.  The comparison operands were previously
-   stored in frv_compare_op0 and frv_compare_op1.
-
+/* Emit code for a conditional branch.
    XXX: I originally wanted to add a clobber of a CCR register to use in
    conditional execution, but that confuses the rest of the compiler.  */
 
 int
-frv_emit_cond_branch (enum rtx_code test, rtx label)
+frv_emit_cond_branch (rtx operands[])
 {
   rtx test_rtx;
   rtx label_ref;
   rtx if_else;
-  rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
+  enum rtx_code test = GET_CODE (operands[0]);
+  rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
   enum machine_mode cc_mode = GET_MODE (cc_reg);
 
   /* Branches generate:
@@ -4751,7 +4745,7 @@ frv_emit_cond_branch (enum rtx_code test
 	     (if_then_else (<test>, <cc_reg>, (const_int 0))
 			    (label_ref <branch_label>)
 			    (pc))) */
-  label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
+  label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
   test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
   if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
   emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
@@ -4759,23 +4753,23 @@ frv_emit_cond_branch (enum rtx_code test
 }
 
 
-/* Emit code to set a gpr to 1/0 based on a comparison.  The comparison
-   operands were previously stored in frv_compare_op0 and frv_compare_op1.  */
+/* Emit code to set a gpr to 1/0 based on a comparison.  */
 
 int
-frv_emit_scc (enum rtx_code test, rtx target)
+frv_emit_scc (rtx operands[])
 {
   rtx set;
   rtx test_rtx;
   rtx clobber;
   rtx cr_reg;
-  rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
+  enum rtx_code test = GET_CODE (operands[1]);
+  rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
 
   /* SCC instructions generate:
 	(parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
 		   (clobber (<ccr_reg>))])  */
   test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
-  set = gen_rtx_SET (VOIDmode, target, test_rtx);
+  set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
 
   cr_reg = ((TARGET_ALLOC_CC)
 	    ? gen_reg_rtx (CC_CCRmode)
@@ -4837,7 +4831,8 @@ frv_emit_cond_move (rtx dest, rtx test_r
   rtx cr_reg;
   rtx if_rtx;
   enum rtx_code test = GET_CODE (test_rtx);
-  rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
+  rtx cc_reg = frv_emit_comparison (test,
+				    XEXP (test_rtx, 0), XEXP (test_rtx, 1));
   enum machine_mode cc_mode = GET_MODE (cc_reg);
 
   /* Conditional move instructions generate: