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Re: [PATCH] s390: z10 scheduler fixes part 3/4
- From: Wolfgang Gellerich <gelleric at linux dot vnet dot ibm dot com>
- To: Andreas Krebbel <krebbel at linux dot vnet dot ibm dot com>
- Cc: GCC-Patches <gcc-patches at gcc dot gnu dot org>
- Date: Fri, 30 Jan 2009 09:34:55 +0100
- Subject: Re: [PATCH] s390: z10 scheduler fixes part 3/4
- References: <49807D2D.6070905@linux.vnet.ibm.com> <49816779.2000003@linux.vnet.ibm.com>
Andreas Krebbel wrote:
Hi Wolfgang,
splitting up the insn is ok with me. It indeed makes it somewhat more
readable.
But I don't think the remaining insv_h* pattern makes sense for 32 bit
anymore and will not be matched anyway:
! (define_insn "*insv_h<mode>_reg_extimm"
[(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
(const_int 32)
(match_operand 1 "const_int_operand" "n"))
(match_operand:P 2 "const_int_operand" "n"))]
"TARGET_EXTIMM
! && BITS_PER_WORD - INTVAL (operands[1]) == 64"
! "iihf\t%0,%o2"
[(set_attr "op_type" "RIL")
(set_attr "z10prop" "z10_fwd_E1")])
I think it better should look like this:
(define_insn "*insv_hdi_reg_extimm"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
(const_int 32)
(const_int 0))
(match_operand:P 2 "const_int_operand" "n"))]
"TARGET_EXTIMM"
"iihf\t%0,%o2"
[(set_attr "op_type" "RIL")
(set_attr "z10prop" "z10_fwd_E1")])
Bye,
-Andreas-
After a few changes, bootstrapping and regression test are now ok for
the patch below.
Regards, Wolfgang
--
---
Dr. Wolfgang Gellerich
IBM Deutschland Entwicklung GmbH
Schönaicher Strasse 220
71032 Böblingen, Germany
Tel. +49 / 7031 / 162598
gellerich@de.ibm.com
=======================
IBM Deutschland Entwicklung GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter
Geschäftsführung: Erich Baier
Sitz der Gesellschaft: Böblingen
Registergericht: Amtsgericht Stuttgart, HRB 243294
Changelog:
2009-01-30 Wolfgang Gellerich <gellerich@de,ibm.com>
* config/s390/s390.md (*insv<mode>_reg_extimm): Removed.
(*insv_h_di_reg_extimm): New insn.
(*insv_l<mode>_reg_extimm): New insn.
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig 2009-01-29 10:41:47.000000000 +0100
--- gcc/config/s390/s390.md 2009-01-29 15:36:54.000000000 +0100
***************
*** 3378,3404 ****
[(set_attr "op_type" "RI")
(set_attr "z10prop" "z10_super_E1")])
! (define_insn "*insv<mode>_reg_extimm"
[(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
(const_int 32)
(match_operand 1 "const_int_operand" "n"))
(match_operand:P 2 "const_int_operand" "n"))]
"TARGET_EXTIMM
! && INTVAL (operands[1]) >= 0
! && INTVAL (operands[1]) < BITS_PER_WORD
! && INTVAL (operands[1]) % 32 == 0"
! {
! switch (BITS_PER_WORD - INTVAL (operands[1]))
! {
! case 64: return "iihf\t%0,%o2"; break;
! case 32: return "iilf\t%0,%o2"; break;
! default: gcc_unreachable();
! }
! }
[(set_attr "op_type" "RIL")
! (set_attr "z10prop" "z10_fwd_E1")])
!
;
; extendsidi2 instruction pattern(s).
--- 3378,3405 ----
[(set_attr "op_type" "RI")
(set_attr "z10prop" "z10_super_E1")])
+ ; Update the left-most 32 bit of a DI.
+ (define_insn "*insv_h_di_reg_extimm"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+ (const_int 32)
+ (const_int 0))
+ (match_operand:DI 1 "const_int_operand" "n"))]
+ "TARGET_EXTIMM"
+ "iihf\t%0,%o1"
+ [(set_attr "op_type" "RIL")
+ (set_attr "z10prop" "z10_fwd_E1")])
! ; Update the right-most 32 bit of a DI, or the whole of a SI.
! (define_insn "*insv_l<mode>_reg_extimm"
[(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
(const_int 32)
(match_operand 1 "const_int_operand" "n"))
(match_operand:P 2 "const_int_operand" "n"))]
"TARGET_EXTIMM
! && BITS_PER_WORD - INTVAL (operands[1]) == 32"
! "iilf\t%0,%o2"
[(set_attr "op_type" "RIL")
! (set_attr "z10prop" "z10_fwd_A1")])
;
; extendsidi2 instruction pattern(s).