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Startup files and link options for powerpc-xilinx-eabi
- From: Michael Eager <eager at eagercon dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 22 Jan 2009 14:04:39 -0800
- Subject: Startup files and link options for powerpc-xilinx-eabi
Attached patch adds link script for powerpc-xilinx-eabi build
and four variants of crt0.o startup files.
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
2009-01-22 Michael Eager <eager@eagercon.com>
* config/rs6000/t-xilinx: New. Linker scripts for powerpc-xilinx-eabi
* config/rs6000/xil-crt0.asm: New. Start-up file.
* config/rs6000/xil-pgcrt0.asm: New. Start-up file.
* config/rs6000/xil-sim-crt0.asm: New. Start-up file.
* config/rs6000/xil-sim-pgcrt0.asm: New. Start-up file.
* config.gcc: Add linker script for powerpc-xilinx-eabi
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn gcc-orig/gcc/config/rs6000/t-xilinx gcc/gcc/config/rs6000/t-xilinx
--- gcc-orig/gcc/config/rs6000/t-xilinx 1969-12-31 16:00:00.000000000 -0800
+++ gcc/gcc/config/rs6000/t-xilinx 2009-01-21 12:14:28.000000000 -0800
@@ -0,0 +1,85 @@
+# Support for Xilinx PowerPC ELF targets
+
+# These can't end up in shared libgcc
+LIB2FUNCS_STATIC_EXTRA = eabi.S
+
+eabi.S: $(srcdir)/config/rs6000/eabi.asm
+ cat $(srcdir)/config/rs6000/eabi.asm > eabi.S
+
+tramp.S: $(srcdir)/config/rs6000/tramp.asm
+ cat $(srcdir)/config/rs6000/tramp.asm > tramp.S
+
+# Switch synonyms
+MULTILIB_MATCHES = mfpu?sp_lite=msingle-float mfpu?dp_lite=mdouble-float mfpu?dp_lite=mhard-float mfpu?sp_lite=mfpu?sp_full mfpu?dp_lite=mfpu?dp_full
+
+MULTILIB_OPTIONS = mfpu=sp_lite/mfpu=dp_lite
+
+MULTILIB_DIRNAMES = single double
+
+MULTILIB_EXTRA_OPTS = mno-eabi mstrict-align mno-relocatable-lib
+
+EXTRA_MULTILIB_PARTS = crtbegin$(objext) crtend$(objext) \
+ crtbeginS$(objext) crtendS$(objext) crtbeginT$(objext) \
+ ecrti$(objext) ecrtn$(objext) \
+ ncrti$(objext) ncrtn$(objext) \
+ xil-crt0$(objext) xil-pgcrt0$(objext) xil-sim-crt0$(objext) \
+ xil-sim-pgcrt0$(objext)
+
+# We build {e,n}crti.o and {e,n}crtn.o, which serve to add begin and
+# end labels to all of the special sections used when we link using gcc.
+
+# Assemble startup files.
+ecrti.S: $(srcdir)/config/rs6000/eabi-ci.asm
+ cat $(srcdir)/config/rs6000/eabi-ci.asm >ecrti.S
+
+ecrtn.S: $(srcdir)/config/rs6000/eabi-cn.asm
+ cat $(srcdir)/config/rs6000/eabi-cn.asm >ecrtn.S
+
+ncrti.S: $(srcdir)/config/rs6000/sol-ci.asm
+ cat $(srcdir)/config/rs6000/sol-ci.asm >ncrti.S
+
+ncrtn.S: $(srcdir)/config/rs6000/sol-cn.asm
+ cat $(srcdir)/config/rs6000/sol-cn.asm >ncrtn.S
+
+xil-crt0.S: $(srcdir)/config/rs6000/xil-crt0.asm
+ cat $(srcdir)/config/rs6000/xil-crt0.asm > xil-crt0.S
+
+xil-pgcrt0.S: $(srcdir)/config/rs6000/xil-pgcrt0.asm
+ cat $(srcdir)/config/rs6000/xil-pgcrt0.asm > xil-pgcrt0.S
+
+xil-sim-crt0.S: $(srcdir)/config/rs6000/xil-sim-crt0.asm
+ cat $(srcdir)/config/rs6000/xil-sim-crt0.asm > xil-sim-crt0.S
+
+xil-sim-pgcrt0.S: $(srcdir)/config/rs6000/xil-sim-pgcrt0.asm
+ cat $(srcdir)/config/rs6000/xil-sim-pgcrt0.asm > xil-sim-pgcrt0.S
+
+# Build multiple copies of ?crt{i,n}.o, one for each target switch.
+$(T)ecrti$(objext): ecrti.S
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c ecrti.S -o $(T)ecrti$(objext)
+
+$(T)ecrtn$(objext): ecrtn.S
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c ecrtn.S -o $(T)ecrtn$(objext)
+
+$(T)ncrti$(objext): ncrti.S
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c ncrti.S -o $(T)ncrti$(objext)
+
+$(T)ncrtn$(objext): ncrtn.S
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c ncrtn.S -o $(T)ncrtn$(objext)
+
+$(T)xil-crt0$(objext): xil-crt0.S
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c xil-crt0.S -o $(T)xil-crt0$(objext)
+
+$(T)xil-pgcrt0$(objext): xil-pgcrt0.S
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c xil-pgcrt0.S -o $(T)xil-pgcrt0$(objext)
+
+$(T)xil-sim-crt0$(objext): xil-sim-crt0.S
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c xil-sim-crt0.S -o $(T)xil-sim-crt0$(objext)
+
+$(T)xil-sim-pgcrt0$(objext): xil-sim-pgcrt0.S
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c xil-sim-pgcrt0.S -o $(T)xil-sim-pgcrt0$(objext)
+
+# It is important that crtbegin.o, etc., aren't surprised by stuff in .sdata.
+CRTSTUFF_T_CFLAGS = -msdata=none
+# Make sure crt*.o are built with -fPIC even if configured with
+# --enable-shared --disable-multilib
+CRTSTUFF_T_CFLAGS_S = -fPIC -msdata=none
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn gcc-orig/gcc/config/rs6000/xil-crt0.asm gcc/gcc/config/rs6000/xil-crt0.asm
--- gcc-orig/gcc/config/rs6000/xil-crt0.asm 1969-12-31 16:00:00.000000000 -0800
+++ gcc/gcc/config/rs6000/xil-crt0.asm 2009-01-21 12:14:28.000000000 -0800
@@ -0,0 +1,168 @@
+/*-----------------------------------------------------------------------------
+// $Date: 2006/03/17 02:10:49 $
+// $RCSfile: xil-crt0.asm,v $
+//-----------------------------------------------------------------------------
+//
+// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
+//
+// Xilinx, Inc.
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+//---------------------------------------------------------------------------*/
+
+ .file "xil-crt0.S"
+ .section ".got2","aw"
+ .align 2
+
+.LCTOC1 = . + 32768
+
+.Lsbss_start = .-.LCTOC1
+ .long __sbss_start
+
+.Lsbss_end = .-.LCTOC1
+ .long __sbss_end
+
+.Lbss_start = .-.LCTOC1
+ .long __bss_start
+
+.Lbss_end = .-.LCTOC1
+ .long __bss_end
+
+.Lstack = .-.LCTOC1
+ .long __stack
+
+.Lsda = .-.LCTOC1
+ .long _SDA_BASE_ /* address of the first small data area */
+
+.Lsda2 = .-.LCTOC1
+ .long _SDA2_BASE_ /* address of the second small data area */
+
+
+ .text
+ .globl _start
+_start:
+ bl __cpu_init /* Initialize the CPU first (BSP provides this) */
+
+ lis 5,.LCTOC1@h
+ ori 5,5,.LCTOC1@l
+
+ lwz 13,.Lsda(5) /* load r13 with _SDA_BASE_ address */
+ lwz 2,.Lsda2(5) /* load r2 with _SDA2_BASE_ address */
+
+ /* clear sbss */
+ lwz 6,.Lsbss_start(5) /* calculate beginning of the SBSS */
+ lwz 7,.Lsbss_end(5) /* calculate end of the SBSS */
+
+ cmplw 1,6,7
+ bc 4,4,.Lenclsbss /* If no SBSS, no clearing required */
+
+ li 0,0 /* zero to clear memory */
+ subf 8,6,7 /* number of bytes to zero */
+ srwi. 9,8,2 /* number of words to zero */
+ beq .Lstbyteloopsbss /* Check if the number of bytes was less than 4 */
+ mtctr 9
+ addi 6,6,-4 /* adjust so we can use stwu */
+.Lloopsbss:
+ stwu 0,4(6) /* zero sbss */
+ bdnz .Lloopsbss
+
+.Lstbyteloopsbss:
+ andi. 9,8,3 /* Calculate how many trailing bytes we have */
+ beq 0,.Lenclsbss
+ mtctr 9
+ addi 6,6,-1 /* adjust, so we can use stbu */
+
+.Lbyteloopsbss:
+ stbu 0,1(6)
+ bdnz .Lbyteloopsbss
+
+.Lenclsbss:
+.Lstclbss:
+
+ /* clear bss */
+ lwz 6,.Lbss_start(5) /* calculate beginning of the BSS */
+ lwz 7,.Lbss_end(5) /* calculate end of the BSS */
+
+ cmplw 1,6,7
+ bc 4,4,.Lenclbss /* If no BSS, no clearing required */
+
+ li 0,0 /* zero to clear memory */
+ subf 8,6,7 /* number of bytes to zero */
+ srwi. 9,8,2 /* number of words to zero */
+ beq .Lstbyteloopbss /* Check if the number of bytes was less than 4 */
+ mtctr 9
+ addi 6,6,-4 /* adjust so we can use stwu */
+.Lloopbss:
+ stwu 0,4(6) /* zero bss */
+ bdnz .Lloopbss
+
+.Lstbyteloopbss:
+ andi. 9,8,3 /* Calculate how many trailing bytes we have */
+ beq 0,.Lenclbss /* If zero, we are done */
+ mtctr 9
+ addi 6,6,-1 /* adjust, so we can use stbu */
+
+.Lbyteloopbss:
+ stbu 0,1(6)
+ bdnz .Lbyteloopbss
+
+.Lenclbss:
+
+ /* set stack pointer */
+ lwz 1,.Lstack(5) /* stack address */
+
+ /* set up initial stack frame */
+ addi 1,1,-8 /* location of back chain */
+ lis 0,0
+ stw 0,0(1) /* set end of back chain */
+
+ /* initialize base timer to zero */
+ mtspr 0x11c,0
+ mtspr 0x11d,0
+
+#ifdef HAVE_XFPU
+ /* On the Xilinx PPC405 and PPC440, the MSR
+ must be explicitly set to mark the prescence
+ of an FPU */
+ mfpvr 0
+ rlwinm 0,0,0,12,15
+ cmpwi 7,0,8192
+ mfmsr 0
+ ori 0,0,8192
+ beq- 7,fpu_init_done
+do_405:
+ oris 0,0,512
+fpu_init_done:
+ mtmsr 0
+#endif
+
+ /* Call __init */
+ bl __init
+
+ /* Let her rip */
+ bl main
+
+ /* Invoke the language cleanup functions */
+ bl __fini
+
+ /* All done */
+ bl exit
+
+/* Trap has been removed for both simulation and hardware */
+ .globl _exit
+_exit:
+ b _exit
+
+.Lstart:
+ .size _start,.Lstart-_start
+
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn gcc-orig/gcc/config/rs6000/xil-pgcrt0.asm gcc/gcc/config/rs6000/xil-pgcrt0.asm
--- gcc-orig/gcc/config/rs6000/xil-pgcrt0.asm 1969-12-31 16:00:00.000000000 -0800
+++ gcc/gcc/config/rs6000/xil-pgcrt0.asm 2009-01-21 12:14:28.000000000 -0800
@@ -0,0 +1,174 @@
+/*-----------------------------------------------------------------------------
+// $Date: 2006/03/17 02:10:49 $
+// $RCSfile: xil-pgcrt0.asm,v $
+//-----------------------------------------------------------------------------
+//
+// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
+//
+// Xilinx, Inc.
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+//---------------------------------------------------------------------------*/
+
+ .file "xil-pgcrt0.S"
+ .section ".got2","aw"
+ .align 2
+
+.LCTOC1 = . + 32768
+
+.Lsbss_start = .-.LCTOC1
+ .long __sbss_start
+
+.Lsbss_end = .-.LCTOC1
+ .long __sbss_end
+
+.Lbss_start = .-.LCTOC1
+ .long __bss_start
+
+.Lbss_end = .-.LCTOC1
+ .long __bss_end
+
+.Lstack = .-.LCTOC1
+ .long __stack
+
+.Lsda = .-.LCTOC1
+ .long _SDA_BASE_ /* address of the first small data area */
+
+.Lsda2 = .-.LCTOC1
+ .long _SDA2_BASE_ /* address of the second small data area */
+
+
+ .text
+ .globl _start
+_start:
+ bl __cpu_init /* Initialize the CPU first (BSP provides this) */
+
+ lis 5,.LCTOC1@h
+ ori 5,5,.LCTOC1@l
+
+ lwz 13,.Lsda(5) /* load r13 with _SDA_BASE_ address */
+ lwz 2,.Lsda2(5) /* load r2 with _SDA2_BASE_ address */
+
+ /* clear sbss */
+ lwz 6,.Lsbss_start(5) /* calculate beginning of the SBSS */
+ lwz 7,.Lsbss_end(5) /* calculate end of the SBSS */
+
+ cmplw 1,6,7
+ bc 4,4,.Lenclsbss /* If no SBSS, no clearing required */
+
+ li 0,0 /* zero to clear memory */
+ subf 8,6,7 /* number of bytes to zero */
+ srwi. 9,8,2 /* number of words to zero */
+ beq .Lstbyteloopsbss /* Check if the number of bytes was less than 4 */
+ mtctr 9
+ addi 6,6,-4 /* adjust so we can use stwu */
+.Lloopsbss:
+ stwu 0,4(6) /* zero sbss */
+ bdnz .Lloopsbss
+
+.Lstbyteloopsbss:
+ andi. 9,8,3 /* Calculate how many trailing bytes we have */
+ beq 0,.Lenclsbss
+ mtctr 9
+ addi 6,6,-1 /* adjust, so we can use stbu */
+
+.Lbyteloopsbss:
+ stbu 0,1(6)
+ bdnz .Lbyteloopsbss
+
+.Lenclsbss:
+.Lstclbss:
+
+ /* clear bss */
+ lwz 6,.Lbss_start(5) /* calculate beginning of the BSS */
+ lwz 7,.Lbss_end(5) /* calculate end of the BSS */
+
+ cmplw 1,6,7
+ bc 4,4,.Lenclbss /* If no BSS, no clearing required */
+
+ li 0,0 /* zero to clear memory */
+ subf 8,6,7 /* number of bytes to zero */
+ srwi. 9,8,2 /* number of words to zero */
+ beq .Lstbyteloopbss /* Check if the number of bytes was less than 4 */
+ mtctr 9
+ addi 6,6,-4 /* adjust so we can use stwu */
+.Lloopbss:
+ stwu 0,4(6) /* zero bss */
+ bdnz .Lloopbss
+
+.Lstbyteloopbss:
+ andi. 9,8,3 /* Calculate how many trailing bytes we have */
+ beq 0,.Lenclbss /* If zero, we are done */
+ mtctr 9
+ addi 6,6,-1 /* adjust, so we can use stbu */
+
+.Lbyteloopbss:
+ stbu 0,1(6)
+ bdnz .Lbyteloopbss
+
+.Lenclbss:
+
+ /* set stack pointer */
+ lwz 1,.Lstack(5) /* stack address */
+
+ /* set up initial stack frame */
+ addi 1,1,-8 /* location of back chain */
+ lis 0,0
+ stw 0,0(1) /* set end of back chain */
+
+ /* initialize base timer to zero */
+ mtspr 0x11c,0
+ mtspr 0x11d,0
+
+#ifdef HAVE_XFPU
+ /* On the Xilinx PPC405 and PPC440, the MSR
+ must be explicitly set to mark the prescence
+ of an FPU */
+ mfpvr 0
+ rlwinm 0,0,0,12,15
+ cmpwi 7,0,8192
+ mfmsr 0
+ ori 0,0,8192
+ beq- 7,fpu_init_done
+do_405:
+ oris 0,0,512
+fpu_init_done:
+ mtmsr 0
+#endif
+
+ /* Setup profiling stuff */
+ bl _profile_init
+
+ /* Call __init */
+ bl __init
+
+ /* Let her rip */
+ bl main
+
+ /* Invoke the language cleanup functions */
+ bl __fini
+
+ /* Cleanup profiling stuff */
+ bl _profile_clean
+
+ /* All done */
+ bl exit
+
+/* Trap has been removed for both simulation and hardware */
+ .globl _exit
+_exit:
+ b _exit
+
+.Lstart:
+ .size _start,.Lstart-_start
+
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn gcc-orig/gcc/config/rs6000/xil-sim-crt0.asm gcc/gcc/config/rs6000/xil-sim-crt0.asm
--- gcc-orig/gcc/config/rs6000/xil-sim-crt0.asm 1969-12-31 16:00:00.000000000 -0800
+++ gcc/gcc/config/rs6000/xil-sim-crt0.asm 2009-01-21 12:14:28.000000000 -0800
@@ -0,0 +1,115 @@
+/*-----------------------------------------------------------------------------
+// $Date: 2005/12/30 00:29:50 $
+// $RCSfile: xil-sim-crt0.asm,v $
+//-----------------------------------------------------------------------------
+//
+// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
+//
+// Xilinx, Inc.
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+//---------------------------------------------------------------------------*/
+
+ .file "xil-sim-crt0.S"
+ .section ".got2","aw"
+ .align 2
+
+.LCTOC1 = . + 32768
+
+.Lsbss_start = .-.LCTOC1
+ .long __sbss_start
+
+.Lsbss_end = .-.LCTOC1
+ .long __sbss_end
+
+.Lbss_start = .-.LCTOC1
+ .long __bss_start
+
+.Lbss_end = .-.LCTOC1
+ .long __bss_end
+
+.Lstack = .-.LCTOC1
+ .long __stack
+
+.Lsda = .-.LCTOC1
+ .long _SDA_BASE_ /* address of the first small data area */
+
+.Lsda2 = .-.LCTOC1
+ .long _SDA2_BASE_ /* address of the second small data area */
+
+ .text
+ .globl _start
+_start:
+ bl __cpu_init /* Initialize the CPU first (BSP provides this */
+
+ lis 5,.LCTOC1@h
+ ori 5,5,.LCTOC1@l
+
+ lwz 13,.Lsda(5) /* load r13 with _SDA_BASE_ address */
+ lwz 2,.Lsda2(5) /* load r2 with _SDA2_BASE_ address */
+
+ /* We don't clear the BSS here.
+ The simulator and the user program need to be aware of this
+
+ ....
+
+ */
+
+ /* set stack pointer */
+ lwz 1,.Lstack(5) /* stack address */
+
+ /* set up initial stack frame */
+ addi 1,1,-8 /* location of back chain */
+ lis 0,0
+ stw 0,0(1) /* set end of back chain */
+
+ /* initialize base timer to zero */
+ mtspr 0x11c,0
+ mtspr 0x11d,0
+
+#ifdef HAVE_XFPU
+ /* On the Xilinx PPC405 and PPC440, the MSR
+ must be explicitly set to mark the prescence
+ of an FPU */
+ mfpvr 0
+ rlwinm 0,0,0,12,15
+ cmpwi 7,0,8192
+ mfmsr 0
+ ori 0,0,8192
+ beq- 7,fpu_init_done
+do_405:
+ oris 0,0,512
+fpu_init_done:
+ mtmsr 0
+#endif
+
+ /* Call __init */
+ bl __init
+
+ /* Let her rip */
+ bl main
+
+ /* Invoke the language cleanup functions */
+ bl __fini
+
+ /* All done */
+ bl exit
+
+/* Trap has been removed for both simulation and hardware */
+ .globl _exit
+_exit:
+ b _exit
+
+.Lstart:
+ .size _start,.Lstart-_start
+
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn gcc-orig/gcc/config/rs6000/xil-sim-pgcrt0.asm gcc/gcc/config/rs6000/xil-sim-pgcrt0.asm
--- gcc-orig/gcc/config/rs6000/xil-sim-pgcrt0.asm 1969-12-31 16:00:00.000000000 -0800
+++ gcc/gcc/config/rs6000/xil-sim-pgcrt0.asm 2009-01-21 12:14:28.000000000 -0800
@@ -0,0 +1,122 @@
+/*-----------------------------------------------------------------------------
+// $Date: 2005/12/30 00:29:50 $
+// $RCSfile: xil-sim-pgcrt0.asm,v $
+//-----------------------------------------------------------------------------
+//
+// Copyright (c) 2004 Xilinx, Inc. All rights reserved.
+//
+// Xilinx, Inc.
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+//---------------------------------------------------------------------------*/
+
+ .file "xil-sim-pgcrt0.S"
+ .section ".got2","aw"
+ .align 2
+
+.LCTOC1 = . + 32768
+
+.Lsbss_start = .-.LCTOC1
+ .long __sbss_start
+
+.Lsbss_end = .-.LCTOC1
+ .long __sbss_end
+
+.Lbss_start = .-.LCTOC1
+ .long __bss_start
+
+.Lbss_end = .-.LCTOC1
+ .long __bss_end
+
+.Lstack = .-.LCTOC1
+ .long __stack
+
+.Lsda = .-.LCTOC1
+ .long _SDA_BASE_ /* address of the first small data area */
+
+.Lsda2 = .-.LCTOC1
+ .long _SDA2_BASE_ /* address of the second small data area */
+
+ .text
+ .globl _start
+_start:
+ bl __cpu_init /* Initialize the CPU first (BSP provides this */
+
+ lis 5,.LCTOC1@h
+ ori 5,5,.LCTOC1@l
+
+ lwz 13,.Lsda(5) /* load r13 with _SDA_BASE_ address */
+ lwz 2,.Lsda2(5) /* load r2 with _SDA2_BASE_ address */
+
+ /* We don't clear the BSS here.
+ The simulator and the user program need to be aware of this
+
+ ....
+
+ */
+
+ /* set stack pointer */
+ lwz 1,.Lstack(5) /* stack address */
+
+ /* set up initial stack frame */
+ addi 1,1,-8 /* location of back chain */
+ lis 0,0
+ stw 0,0(1) /* set end of back chain */
+
+ /* initialize base timer to zero */
+ mtspr 0x11c,0
+ mtspr 0x11d,0
+
+#ifdef HAVE_XFPU
+ /* On the Xilinx PPC405 and PPC440, the MSR
+ must be explicitly set to mark the prescence
+ of an FPU */
+ mfpvr 0
+ rlwinm 0,0,0,12,15
+ cmpwi 7,0,8192
+ mfmsr 0
+ ori 0,0,8192
+ beq- 7,fpu_init_done
+do_405:
+ oris 0,0,512
+fpu_init_done:
+ mtmsr 0
+#endif
+
+ /* Setup profiling stuff */
+ bl _profile_init
+
+ /* Call __init */
+ bl __init
+
+ /* Let her rip */
+ bl main
+
+ /* Invoke the language cleanup functions */
+ bl __fini
+
+ /* Cleanup profiling stuff */
+ bl _profile_clean
+
+ /* All done */
+ bl exit
+
+
+/* Trap has been removed for both simulation and hardware */
+ .globl _exit
+_exit:
+ b _exit
+
+.Lstart:
+ .size _start,.Lstart-_start
+
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn gcc-orig/gcc/config.gcc gcc/gcc/config.gcc
--- gcc-orig/gcc/config.gcc 2009-01-21 12:13:06.000000000 -0800
+++ gcc/gcc/config.gcc 2009-01-21 12:14:28.000000000 -0800
@@ -1791,7 +1791,7 @@ powerpc-*-eabialtivec*)
powerpc-xilinx-eabi*)
tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h"
extra_options="${extra_options} rs6000/sysv4.opt"
- tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
+ tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-xilinx"
;;
powerpc-*-eabi*)
tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h"