This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[committed] Fix FPR moves for -mfp32 -mips64r2
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Mon, 15 Dec 2008 21:10:40 +0000
- Subject: [committed] Fix FPR moves for -mfp32 -mips64r2
Thie patch follows on from the fix for PR target/37362. When generating
-mfp32 code on MIPS64r2 targets, we'd wrongly use MTHC1 and MFHC1 to
split a 64-bit FPR move.
Tested on mips64el-linux-gnu and applied. We'll get testsuite coverage
after I commit the pending mips.exp changes.
Richard
gcc/
* config/mips/mips.md (move_doubleword_fpr<mode>): Use
TARGET_FLOAT64 && !TARGET_64BIT to detect the mxhc1 case.
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md 2008-12-13 14:39:15.000000000 +0000
+++ gcc/config/mips/mips.md 2008-12-13 15:38:10.000000000 +0000
@@ -4521,8 +4521,8 @@ (define_expand "move_doubleword_fpr<mode
rtx low = mips_subword (operands[1], 0);
rtx high = mips_subword (operands[1], 1);
emit_insn (gen_load_low<mode> (operands[0], low));
- if (ISA_HAS_MXHC1 && reg_or_0_operand (high, <HALFMODE>mode))
- emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
+ if (TARGET_FLOAT64 && !TARGET_64BIT)
+ emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
else
emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
}
@@ -4531,7 +4531,7 @@ (define_expand "move_doubleword_fpr<mode
rtx low = mips_subword (operands[0], 0);
rtx high = mips_subword (operands[0], 1);
emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
- if (ISA_HAS_MXHC1 && register_operand (high, <HALFMODE>mode))
+ if (TARGET_FLOAT64 && !TARGET_64BIT)
emit_insn (gen_mfhc1<mode> (high, operands[1]));
else
emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));