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[Committed] S/390: Remove mem->mem alternative from int mode move patterns
- From: "Andreas Krebbel" <krebbel at linux dot vnet dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Ulrich dot Weigand at de dot ibm dot com
- Date: Tue, 9 Dec 2008 10:11:34 +0100
- Subject: [Committed] S/390: Remove mem->mem alternative from int mode move patterns
Hello,
since its very beginning the S/390 back end implemented integer mode
moves between two memory locations with a memcpy instruction.
Therefore we provided a Q->Q alternative in the mov patterns together
with a splitter which turns the integer mode move into a BLKmode move.
This never has been a problem so far. As discussed in the GCC irc
channel this is not correct since e.g. a movsi pattern is expected to
completely read the source operand before writing anything into the
target operand. This leads to problems when the two operands are
overlapping memory locations. In this case it is incorrect to
implement the move with a memcpy instruction copying byte after byte.
The problem is revealed by the recent changes to
fold_builtin_memory_op which enables folding also for the
gcc.dg/pr35258.c testcase:
char string2[9] = "1234";
void
foo (void)
{
char temp[4];
char *p = &string2[2];
memcpy (&temp, &string2[1], 4);
memcpy (p, &temp, 4);
string2[1] = '.';
}
The attached patch removes the mem->mem alternatives for all move
patterns together with the splitter. Performance measurements show
that we lose about 1% performance with that change. I'll try to get
the 1% back turning the old splitter into a pre-reload splitter
checking for trivially non-overlapping memcpys in the insn condition.
I'll post the patch in case the numbers look good.
Patch committed to mainline.
Bye,
-Andreas-
2008-12-09 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md (movti, movdi_64, movdi_31,
*movsi_zarch, *movhi, *movqi, *mov<mode>_64, *mov<mode>_31,
*mov<mode>_64dfp, *mov<mode>_64, *mov<mode>_31, mov<mode>): Remove
Q->Q alternative.
(Integer->BLKmode splitter): Removed.
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig 2008-12-01 11:03:17.000000000 +0100
--- gcc/config/s390/s390.md 2008-12-02 12:36:25.000000000 +0100
***************
*** 1081,1097 ****
;
(define_insn "movti"
! [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
! (match_operand:TI 1 "general_operand" "QS,d,dPRT,d,Q"))]
"TARGET_64BIT"
"@
lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0
#
- #
#"
! [(set_attr "op_type" "RSY,RSY,*,*,SS")
! (set_attr "type" "lm,stm,*,*,*")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
--- 1081,1096 ----
;
(define_insn "movti"
! [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
! (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
"TARGET_64BIT"
"@
lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0
#
#"
! [(set_attr "op_type" "RSY,RSY,*,*")
! (set_attr "type" "lm,stm,*,*")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
***************
*** 1273,1282 ****
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
! RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,?Q")
(match_operand:DI 1 "general_operand"
"K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
! d,*f,R,T,*f,*f,d,K,t,d,t,Q,?Q"))]
"TARGET_64BIT"
"@
lghi\t%0,%h1
--- 1272,1281 ----
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
! RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
(match_operand:DI 1 "general_operand"
"K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
! d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
"TARGET_64BIT"
"@
lghi\t%0,%h1
***************
*** 1304,1319 ****
#
#
stam\t%1,%N1,%S0
! lam\t%0,%N0,%S1
! #"
[(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
! RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,SS")
(set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
! *,*,*")
(set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
z10,*,*,*,*,*,longdisp,*,longdisp,
! z10,z10,*,*,*,*,*")
(set_attr "z10prop" "z10_fwd_A1,
z10_fwd_E1,
z10_fwd_E1,
--- 1303,1317 ----
#
#
stam\t%1,%N1,%S0
! lam\t%0,%N0,%S1"
[(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
! RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
(set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
! *,*")
(set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
z10,*,*,*,*,*,longdisp,*,longdisp,
! z10,z10,*,*,*,*")
(set_attr "z10prop" "z10_fwd_A1,
z10_fwd_E1,
z10_fwd_E1,
***************
*** 1339,1345 ****
*,
*,
*,
- *,
*")
])
--- 1337,1342 ----
***************
*** 1378,1386 ****
(define_insn "*movdi_31"
[(set (match_operand:DI 0 "nonimmediate_operand"
! "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,Q,d")
(match_operand:DI 1 "general_operand"
! " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,Q,b"))]
"!TARGET_64BIT"
"@
lm\t%0,%N0,%S1
--- 1375,1383 ----
(define_insn "*movdi_31"
[(set (match_operand:DI 0 "nonimmediate_operand"
! "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
(match_operand:DI 1 "general_operand"
! " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
"!TARGET_64BIT"
"@
lm\t%0,%N0,%S1
***************
*** 1394,1404 ****
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
- #
#"
! [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS,*")
! (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*")
! (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,*,z10")])
; For a load from a symbol ref we can use one of the target registers
; together with larl to load the address.
--- 1391,1400 ----
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
#"
! [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
! (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
! (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
; For a load from a symbol ref we can use one of the target registers
; together with larl to load the address.
***************
*** 1533,1541 ****
(define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
! "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,?Q")
(match_operand:SI 1 "general_operand"
! "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q,?Q"))]
"TARGET_ZARCH"
"@
lhi\t%0,%h1
--- 1529,1537 ----
(define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
! "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
(match_operand:SI 1 "general_operand"
! "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
"TARGET_ZARCH"
"@
lhi\t%0,%h1
***************
*** 1559,1568 ****
stam\t%1,%1,%S0
strl\t%1,%0
mvhi\t%0,%1
! lam\t%0,%0,%S1
! #"
[(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
! RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,SS")
(set_attr "type" "*,
*,
*,
--- 1555,1563 ----
stam\t%1,%1,%S0
strl\t%1,%0
mvhi\t%0,%1
! lam\t%0,%0,%S1"
[(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
! RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
(set_attr "type" "*,
*,
*,
***************
*** 1584,1593 ****
*,
larl,
*,
- *,
*")
(set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
! *,*,longdisp,*,longdisp,*,*,*,z10,z10,*,*")
(set_attr "z10prop" "z10_fwd_A1,
z10_fwd_E1,
z10_fwd_E1,
--- 1579,1587 ----
*,
larl,
*,
*")
(set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
! *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
(set_attr "z10prop" "z10_fwd_A1,
z10_fwd_E1,
z10_fwd_E1,
***************
*** 1609,1620 ****
*,
z10_rec,
z10_super,
- *,
*")])
(define_insn "*movsi_esa"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
! (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
"!TARGET_ZARCH"
"@
lhi\t%0,%h1
--- 1603,1613 ----
*,
z10_rec,
z10_super,
*")])
(define_insn "*movsi_esa"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
! (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
"!TARGET_ZARCH"
"@
lhi\t%0,%h1
***************
*** 1627,1636 ****
ear\t%0,%1
sar\t%0,%1
stam\t%1,%1,%S0
! lam\t%0,%0,%S1
! #"
! [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
! (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")
(set_attr "z10prop" "z10_fwd_A1,
z10_fr_E1,
z10_fwd_A3,
--- 1620,1628 ----
ear\t%0,%1
sar\t%0,%1
stam\t%1,%1,%S0
! lam\t%0,%0,%S1"
! [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
! (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
(set_attr "z10prop" "z10_fwd_A1,
z10_fr_E1,
z10_fwd_A3,
***************
*** 1641,1647 ****
z10_super_E1,
z10_super,
*,
- *,
*")
])
--- 1633,1638 ----
***************
*** 1752,1759 ****
})
(define_insn "*movhi"
! [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,?Q")
! (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,?Q"))]
""
"@
lr\t%0,%1
--- 1743,1750 ----
})
(define_insn "*movhi"
! [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
! (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
""
"@
lr\t%0,%1
***************
*** 1764,1774 ****
sth\t%1,%0
sthy\t%1,%0
sthrl\t%1,%0
! mvhhi\t%0,%1
! #"
! [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,SS")
! (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*")
! (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,*")
(set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1,
z10_super_E1,
--- 1755,1764 ----
sth\t%1,%0
sthy\t%1,%0
sthrl\t%1,%0
! mvhhi\t%0,%1"
! [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
! (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
! (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
(set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1,
z10_super_E1,
***************
*** 1777,1784 ****
z10_super,
z10_rec,
z10_rec,
! z10_super,
! *")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
--- 1767,1773 ----
z10_super,
z10_rec,
z10_rec,
! z10_super")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
***************
*** 1813,1820 ****
})
(define_insn "*movqi"
! [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
! (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
""
"@
lr\t%0,%1
--- 1802,1809 ----
})
(define_insn "*movqi"
! [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
! (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
""
"@
lr\t%0,%1
***************
*** 1824,1833 ****
stc\t%1,%0
stcy\t%1,%0
mvi\t%S0,%b1
! mviy\t%S0,%b1
! #"
! [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
! (set_attr "type" "lr,*,*,*,store,store,store,store,*")
(set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1,
z10_super_E1,
--- 1813,1821 ----
stc\t%1,%0
stcy\t%1,%0
mvi\t%S0,%b1
! mviy\t%S0,%b1"
! [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
! (set_attr "type" "lr,*,*,*,store,store,store,store")
(set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1,
z10_super_E1,
***************
*** 1835,1842 ****
z10_super,
z10_rec,
z10_super,
! z10_super,
! *")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
--- 1823,1829 ----
z10_super,
z10_rec,
z10_super,
! z10_super")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
***************
*** 1905,1912 ****
"")
(define_insn "*mov<mode>_64"
! [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o,Q")
! (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d,Q"))]
"TARGET_64BIT"
"@
lzxr\t%0
--- 1892,1899 ----
"")
(define_insn "*mov<mode>_64"
! [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
! (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
"TARGET_64BIT"
"@
lzxr\t%0
***************
*** 1916,1938 ****
lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0
#
- #
#"
! [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*")
! (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*,*")])
(define_insn "*mov<mode>_31"
! [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,Q")
! (match_operand:TD_TF 1 "general_operand" " G,f,o,f,Q"))]
"!TARGET_64BIT"
"@
lzxr\t%0
lxr\t%0,%1
#
- #
#"
! [(set_attr "op_type" "RRE,RRE,*,*,*")
! (set_attr "type" "fsimptf,fsimptf,*,*,*")])
; TFmode in GPRs splitters
--- 1903,1923 ----
lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0
#
#"
! [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
! (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")])
(define_insn "*mov<mode>_31"
! [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
! (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
"!TARGET_64BIT"
"@
lzxr\t%0
lxr\t%0,%1
#
#"
! [(set_attr "op_type" "RRE,RRE,*,*")
! (set_attr "type" "fsimptf,fsimptf,*,*")])
; TFmode in GPRs splitters
***************
*** 2023,2031 ****
(define_insn "*mov<mode>_64dfp"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
! "=f,f,f,d,f,f,R,T,d,d,RT,?Q")
(match_operand:DD_DF 1 "general_operand"
! "G,f,d,f,R,T,f,f,d,RT,d,?Q"))]
"TARGET_64BIT && TARGET_DFP"
"@
lzdr\t%0
--- 2008,2016 ----
(define_insn "*mov<mode>_64dfp"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
! "=f,f,f,d,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand"
! " G,f,d,f,R,T,f,f,d,RT, d"))]
"TARGET_64BIT && TARGET_DFP"
"@
lzdr\t%0
***************
*** 2038,2048 ****
stdy\t%1,%0
lgr\t%0,%1
lg\t%0,%1
! stg\t%1,%0
! #"
! [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
(set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
! fstoredf,fstoredf,lr,load,store,*")
(set_attr "z10prop" "*,
*,
*,
--- 2023,2032 ----
stdy\t%1,%0
lgr\t%0,%1
lg\t%0,%1
! stg\t%1,%0"
! [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
(set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
! fstoredf,fstoredf,lr,load,store")
(set_attr "z10prop" "*,
*,
*,
***************
*** 2053,2065 ****
*,
z10_fr_E1,
z10_fwd_A3,
! z10_rec,
! *")
])
(define_insn "*mov<mode>_64"
! [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT,?Q")
! (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d,?Q"))]
"TARGET_64BIT"
"@
lzdr\t%0
--- 2037,2048 ----
*,
z10_fr_E1,
z10_fwd_A3,
! z10_rec")
])
(define_insn "*mov<mode>_64"
! [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
! (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
"TARGET_64BIT"
"@
lzdr\t%0
***************
*** 2070,2080 ****
stdy\t%1,%0
lgr\t%0,%1
lg\t%0,%1
! stg\t%1,%0
! #"
! [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
(set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
! fstore<mode>,fstore<mode>,lr,load,store,*")
(set_attr "z10prop" "*,
*,
*,
--- 2053,2062 ----
stdy\t%1,%0
lgr\t%0,%1
lg\t%0,%1
! stg\t%1,%0"
! [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
(set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
! fstore<mode>,fstore<mode>,lr,load,store")
(set_attr "z10prop" "*,
*,
*,
***************
*** 2083,2096 ****
*,
z10_fr_E1,
z10_fwd_A3,
! z10_rec,
! *")])
(define_insn "*mov<mode>_31"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
! "=f,f,f,f,R,T,d,d,Q,S, d,o,Q")
(match_operand:DD_DF 1 "general_operand"
! " G,f,R,T,f,f,Q,S,d,d,dPRT,d,Q"))]
"!TARGET_64BIT"
"@
lzdr\t%0
--- 2065,2077 ----
*,
z10_fr_E1,
z10_fwd_A3,
! z10_rec")])
(define_insn "*mov<mode>_31"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
! "=f,f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand"
! " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
"!TARGET_64BIT"
"@
lzdr\t%0
***************
*** 2104,2114 ****
stm\t%1,%N1,%S0
stmy\t%1,%N1,%S0
#
- #
#"
! [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
(set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
! fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*,*")])
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
--- 2085,2094 ----
stm\t%1,%N1,%S0
stmy\t%1,%N1,%S0
#
#"
! [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
(set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
! fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
***************
*** 2157,2165 ****
(define_insn "mov<mode>"
[(set (match_operand:SD_SF 0 "nonimmediate_operand"
! "=f,f,f,f,R,T,d,d,d,R,T,?Q")
(match_operand:SD_SF 1 "general_operand"
! " G,f,R,T,f,f,d,R,T,d,d,?Q"))]
""
"@
lzer\t%0
--- 2137,2145 ----
(define_insn "mov<mode>"
[(set (match_operand:SD_SF 0 "nonimmediate_operand"
! "=f,f,f,f,R,T,d,d,d,R,T")
(match_operand:SD_SF 1 "general_operand"
! " G,f,R,T,f,f,d,R,T,d,d"))]
""
"@
lzer\t%0
***************
*** 2172,2182 ****
l\t%0,%1
ly\t%0,%1
st\t%1,%0
! sty\t%1,%0
! #"
! [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
! fstore<mode>,fstore<mode>,lr,load,load,store,store,*")
(set_attr "z10prop" "*,
*,
*,
--- 2152,2161 ----
l\t%0,%1
ly\t%0,%1
st\t%1,%0
! sty\t%1,%0"
! [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
(set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
! fstore<mode>,fstore<mode>,lr,load,load,store,store")
(set_attr "z10prop" "*,
*,
*,
***************
*** 2187,2194 ****
z10_fwd_A3,
z10_fwd_A3,
z10_super,
! z10_rec,
! *")])
;
; movcc instruction pattern
--- 2166,2172 ----
z10_fwd_A3,
z10_fwd_A3,
z10_super,
! z10_rec")])
;
; movcc instruction pattern
***************
*** 2222,2242 ****
"mvc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")])
- (define_split
- [(set (match_operand 0 "memory_operand" "")
- (match_operand 1 "memory_operand" ""))]
- "reload_completed
- && GET_MODE (operands[0]) == GET_MODE (operands[1])
- && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
- [(parallel
- [(set (match_dup 0) (match_dup 1))
- (use (match_dup 2))])]
- {
- operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
- operands[0] = adjust_address (operands[0], BLKmode, 0);
- operands[1] = adjust_address (operands[1], BLKmode, 0);
- })
-
(define_peephole2
[(parallel
[(set (match_operand:BLK 0 "memory_operand" "")
--- 2200,2205 ----