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Re: Workaround Cortex-M3 silicon errata
- From: Gerald Pfeifer <gerald at pfeifer dot com>
- To: Paul Brook <paul at codesourcery dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Sat, 15 Nov 2008 15:14:56 +0100 (CET)
- Subject: Re: Workaround Cortex-M3 silicon errata
- References: <firstname.lastname@example.org>
On Thu, 13 Nov 2008, Paul Brook wrote:
> Many Cortex-M3 CPU cores suffer from a design flaw that can cause data
> corruption when the first destination and base register of an ldrd
> instruction overlap (e.g. ldrd r0, [r0]). The patch below adds a new option
> to avoid these problematic cases, and enables it by default
> when -mcpu=cortex-M3 is specified.
Would you mind adding a short note to gcc-4.4/changes.html as well?