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Re: [PATCH,rs6000] fix ICE caused by lax rs6000_legitimize_address




Sent from my iPhone

On Nov 10, 2008, at 8:14 PM, Nathan Froyd <froydnj@codesourcery.com> wrote:

The patch below fixes a mismatch between what rs6000_legitimize_address
generates and what rs6000_legitimate_address_p expects. REG+OFFSET
addressing on ppc64 requires that OFFSET be word-aligned;
rs6000_legitimate_address_p checks for that, rs6000_legitimize_address
did not.


The fix is straightforward enough; I think the check for DDmode is
right, although I don't have a hard decimal-float machine to test on.
Testing in progress on powerpc64-unknown-linux-gnu. OK to commit during
stage 3, or should this wait for 4.5?


-Nathan

Index: gcc/ChangeLog
===================================================================
--- gcc/ChangeLog    (revision 141763)
+++ gcc/ChangeLog    (working copy)
@@ -1,3 +1,8 @@
+2008-11-10  Nathan Froyd  <froydnj@codesourcery.com>
+
+    * config/rs6000/rs6000.c (rs6000_legitimize_address): Check for
+    non-word-aligned REG+CONST addressing.
+
2008-11-10  Catherine Moore  <clm@codesourcery.com>

   * config.gcc (mips64vrel-*-elf*): Include the tm_file
Index: gcc/testsuite/ChangeLog
===================================================================
--- gcc/testsuite/ChangeLog    (revision 141763)
+++ gcc/testsuite/ChangeLog    (working copy)
@@ -1,3 +1,7 @@
+2008-11-10  Nathan Froyd  <froydnj@codesourcery.com>
+
+    * gcc.target/powerpc/20081110-1.c: New test.

Is there a reason why you put this testcase in the target specific part of the testsuite rather than the torture tests? There does not seem like anything target specific in it.


Also please send the changelog as plain text and not part of the patch.

Thanks,
Andrew Pinski


+ 2008-11-10 Catherine Moore <clm@codesourcery.com>

* gcc.target/mips/no-smartmips-lwxs.c: New test.
Index: gcc/testsuite/gcc.target/powerpc/20081110-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/20081110-1.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/20081110-1.c (revision 0)
@@ -0,0 +1,28 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O1" } */
+
+/* Verify that we don't ICE by forming invalid addresses for unaligned
+ doubleword loads. */
+
+struct a
+{
+ unsigned int x;
+ unsigned short y;
+} __attribute__((packed));
+
+struct b {
+ struct a rep;
+ unsigned long long seq;
+} __attribute__((packed));
+
+struct c {
+ int x;
+ struct a a[5460];
+ struct b b;
+};
+
+extern void use_ull(unsigned long long);
+extern void f(struct c *i) {
+ use_ull(i->b.seq);
+ return;
+}
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 141763)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -3816,7 +3816,14 @@ rs6000_legitimize_address (rtx x, rtx ol
high_int = INTVAL (XEXP (x, 1)) - low_int;
sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
GEN_INT (high_int)), 0);
- return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
+ /* Using a REG+CONST 64-bit integer load on 64-bit platforms
+ requires that CONST be word-aligned. */
+ if (TARGET_POWERPC64
+ && (mode == DImode || mode == DDmode)
+ && (low_int & 0x3))
+ return gen_rtx_PLUS (Pmode, sum, force_reg (Pmode, GEN_INT (low_int)));
+ else
+ return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
}
else if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 0)) == REG


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