Re: [patch] Fix FAIL of gcc.target/sparc/pdist-3.c (PR 35574)

[Eric Botcazou <ebotcazou at adacore dot com>]

> It turns out that the invalid insn comes from CSE, which generates a
> load of a vector constant to a register like so:
>
> (set (reg:V8QI 108)
>      (const_vector:V8QI [(const_int 1 [0x1])
> 			 (const_int 2 [0x2])
> 			 (const_int 3 [0x3])
> 			 (const_int 4 [0x4])
> 			 (const_int 5 [0x5])
> 			 (const_int 6 [0x6])
> 			 (const_int 7 [0x7])
> 			 (const_int -1 [0xffffffffffffffff])]))
>
> Before CSE, we have a fully recognizable insn sequence, where we first
> load into a register the address of the location where a vector
> constant is stored and then "dereference" the pointer to the vector
> constant.
>
> The problem is that the new insn that CSE generates satisfies the
> operand predicates of *movdf_insn_sp32_v9, but it does not satisfy the
> operand constraints.  So, reload attempts to replace the constant with
> (mem (symbol_ref)), but SPARC cannot do (set (reg) (mem
> (symbol_ref))).  Hence the ICE.

Thanks for the analysis.

> The patch fixes this problem by teaching input_operand to accept no
> vector or float constant other than 0, which we can load directly into
> a register with no problem.

This is a pessimization as we can load FP constants into integer integers:

;; This pattern build DFmode constants in integer registers.
(define_split
  [(set (match_operand:DF 0 "register_operand" "")
        (match_operand:DF 1 "const_double_operand" ""))]
  "TARGET_FPU
   && (GET_CODE (operands[0]) == REG
       && REGNO (operands[0]) < 32)
   && ! const_zero_operand(operands[1], DFmode)
   && reload_completed"
  [(clobber (const_int 0))]

> 2008-10-03  Kazu Hirata  <kazu@codesourcery.com>
>
> 	* gcc/config/sparc/predicates.md (input_operand): Do not accept
> 	CONST_DOUBLE or CONST_VECTOR other than 0.

The proper fix is to generalize the aforementioned splitter to all V64 modes 
and add a new constraint similar to F for integral vector constants (if it 
doesn't already exist).

I've not written anything for PR target/35574 yet so, if you want to give it a  
try, please reassign it to you.

-- 
Eric Botcazou