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[committed] Add !TARGET_MIPS16 to Octeon ISA_HAS_* macros
- From: Adam Nemet <anemet at caviumnetworks dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 26 Sep 2008 16:40:17 -0700
- Subject: [committed] Add !TARGET_MIPS16 to Octeon ISA_HAS_* macros
This was a change preapproved by Richard here:
http://gcc.gnu.org/ml/gcc-patches/2008-08/msg02344.html
Bootstrapped and tested on mips64octeon-unknown-linux-gnu.
I already had NOMIPS16 on all functions in the Octeon tests. To be sure I
hadn't missed anything I tested mips.exp=octeon*.c with -mabi=32 -mips16.
Committed as r140714.
2008-09-26 Adam Nemet <anemet@caviumnetworks.com>
* config/mips/mips.h (ISA_HAS_DMUL3, ISA_HAS_BADDU, ISA_HAS_BBIT,
ISA_HAS_CINS, ISA_HAS_EXTS, ISA_HAS_SEQ_SNE, ISA_HAS_POP): Change
them to yield false with MIPS16.
Index: config/mips/mips.h
===================================================================
--- config/mips/mips.h (revision 140713)
+++ config/mips/mips.h (revision 140714)
@@ -783,7 +783,9 @@ enum mips_code_readable_setting {
&& !TARGET_MIPS16)
/* ISA has a three-operand multiplication instruction. */
-#define ISA_HAS_DMUL3 (TARGET_64BIT && TARGET_OCTEON)
+#define ISA_HAS_DMUL3 (TARGET_64BIT \
+ && TARGET_OCTEON \
+ && !TARGET_MIPS16)
/* ISA has the floating-point conditional move instructions introduced
in mips4. */
@@ -1011,22 +1013,22 @@ enum mips_code_readable_setting {
: ISA_HAS_LL_SC)
/* ISA includes the baddu instruction. */
-#define ISA_HAS_BADDU TARGET_OCTEON
+#define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
/* ISA includes the bbit* instructions. */
-#define ISA_HAS_BBIT TARGET_OCTEON
+#define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
/* ISA includes the cins instruction. */
-#define ISA_HAS_CINS TARGET_OCTEON
+#define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
/* ISA includes the exts instruction. */
-#define ISA_HAS_EXTS TARGET_OCTEON
+#define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
/* ISA includes the seq and sne instructions. */
-#define ISA_HAS_SEQ_SNE TARGET_OCTEON
+#define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
/* ISA includes the pop instruction. */
-#define ISA_HAS_POP TARGET_OCTEON
+#define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
/* The CACHE instruction is available in non-MIPS16 code. */
#define TARGET_CACHE_BUILTIN (mips_isa >= 3)