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Re: PowerPC -- support single-precision FPU
- From: Michael Eager <eager at eagercon dot com>
- To: David Edelsohn <dje dot gcc at gmail dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>, Andrew Pinski <pinskia at gmail dot com>
- Date: Sun, 21 Sep 2008 13:47:06 -0700
- Subject: Re: PowerPC -- support single-precision FPU
- References: <303e1d290809211332xeef7c80td56cd7fa113898e1@mail.gmail.com>
David Edelsohn wrote:
Michael Eager writes:
Should floatsisf2_internal have the same constraints as floatdidf2?
Yes.
The condition for floatsisf2_internal should also be changed to
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT"
so that it is only matched for -fsingle-float and not for -fdouble-float
or classic PowerPC FPU.
The floatsisf2_internal pattern also needs TARGET_POWERPC64 condition.
fcfid only is present
on processors that implement PowerPC64.
Is the floatsisf2_internal pattern even necessary? Is that RTL and
instruction ever generated
for the Xilinx configuration?
I'll move this into the Xilinx FPU-specific patch, conditioned with
the flag for that FPU. Xilinx reused the opcode for their SI->SF
conversion instruction.
The floatsisf2 define_expand pattern has final condition !TARGET_FPRS,
which was intended
for SPE and is false for the Xilinx processor.
Yep.
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077