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Re: [pending commit] Work around r10k errata


Richard Sandiford <rdsandiford@googlemail.com> writes:
> gcc/
> 2008-xx-xx  Richard Sandiford  <richard@codesourcery.com>
> 	    Peter Fuerst  <post@pfrst.de>
>
> 	* doc/invoke.texi: Document -mr10k-cache-barrier=.
> 	* doc/extend.texi: Document __builtin_mips_cache.
> 	* config/mips/mips-ftypes.def: Add a (VOID, SI, CVPOINTER) entry.
> 	* config/mips/mips.opt (mr10k-cache-barrier=): New option.
> 	* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
> 	__GCC_HAVE_BUILTIN_MIPS_CACHE.
> 	(TARGET_CACHE_BUILTIN, ISA_HAS_CACHE): New macros.
> 	* config/mips/mips.c (mips_r10k_cache_barrier_setting): New enum.
> 	(set_push_mips_isas): New variable.
> 	(mips_r10k_cache_barrier): New variable.
> 	(cache): New availability predicate.
> 	(mips_builtins): Add an entry for __builtin_mips_cache.
> 	(mips_build_cvpointer_type): New function.
> 	(MIPS_ATYPE_CVPOINTER): New macro.
> 	(mips_prepare_builtin_arg): Only use the insn's mode if the rtx's
> 	mode is VOIDmode.
> 	(r10k_simplified_address_p, r10k_simplify_address)
> 	(r10k_uncached_address_p, r10k_safe_address_p)
> 	(r10k_needs_protection_p_1, r10k_needs_protection_p_store)
> 	(r10k_needs_protection_p_call, r10k_needs_protection_p)
> 	(r10k_insert_cache_barriers): New functions.
> 	(mips_reorg_process_insns): Delete cache barriers after a
> 	branch-likely instruction.
> 	(mips_reorg): Call r10k_insert_cache_barriers.
> 	(mips_handle_option): Handle OPT_mr10k_cache_barrier_.
> 	* config/mips/mips.md (UNSPEC_MIPS_CACHE): New constant.
> 	(UNSPEC_R10K_CACHE_BARRIER): Likewise.
> 	(mips_cache, r10k_cache_barrier): New define_insns.
>
> gcc/testsuite/
> 	* gcc.target/mips/mips.exp (dg-mips-options): Make
> 	-mr10k-cache-barrier=* imply -mips3 or above.
> 	* gcc.target/mips/cache-1.c: New test.
> 	* gcc.target/mips/r10k-cache-barrier-1.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-2.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-3.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-4.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-5.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-6.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-7.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-8.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-9.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-10.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-11.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-12.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-13.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-14.c: Likewise.
> 	* gcc.target/mips/r10k-cache-barrier-15.c: Likewise.

Now applied, after correcting my email address.

(Oops!  For the record, this was all written after I left CS.
The problem is that I use a commit script that applies change logs
and adds the email line for me, so I only have to write the header
when extra attribution is needed.  In those cases, I tend to get
lazy and copy-&-paste.  I obviously didn't copy the right thing
here though.)

I applied the patch below to the list of GCC 4.4 changes.

Richard


Index: htdocs/gcc-4.4/changes.html
===================================================================
--- htdocs/gcc-4.4/changes.html	31 Aug 2008 01:15:33 -0000	1.23
+++ htdocs/gcc-4.4/changes.html	6 Sep 2008 08:15:03 -0000
@@ -197,6 +197,9 @@
         instead of relying on a <code>libgcc</code> function.</li>
     <li>Native GNU/Linux toolchains now support <code>-march=native</code>
         and <code>-mtune=native</code>, which select the host processor.</li>
+    <li>GCC can now work around the side effects of speculative execution
+        on R10K processors.  Please see the documentation of the
+        <code>-mr10k-cache-barrier</code> option for details.</li>
   </ul>
 
 <h2>Documentation improvements</h2>


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