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Blackfin: some new silicon revisions

This patch by Mike Frysinger adds a couple new silicon revisions to the list of Blackfin CPU types. Committed.


Bernd
--
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Geschaeftsfuehrer Thomas Wessel, William A. Martin, Margaret Seif

Index: ChangeLog
===================================================================
--- ChangeLog	(revision 139933)
+++ ChangeLog	(working copy)
@@ -1,3 +1,10 @@
+2008-09-03  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	From Michael Frysinger  <michael.frysinger@analog.com>
+	* config/bfin/bfin.c (bfin_cpus[]): Add 0.1 for bf522, bf523, bf524,
+	bf525, bf526, bf527, bf542, bf544, bf547, bf548, and bf549.  Add 0.2
+	for bf538.
+
 2008-09-03  Hari Sandanagobalane  <hariharan@picochip.com>
 
 	Add picoChip port.
Index: testsuite/ChangeLog
===================================================================
--- testsuite/ChangeLog	(revision 139886)
+++ testsuite/ChangeLog	(working copy)
@@ -1,3 +1,18 @@
+2008-09-03  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	From Mike Frysinger  <michael.frysinger@analog.com>
+	* gcc.target/bfin/mcpu-bf522.c: Check SILICON_REVISION is 0x0001.
+	* gcc.target/bfin/mcpu-bf523.c: Likewise.
+	* gcc.target/bfin/mcpu-bf524.c: Likewise.
+	* gcc.target/bfin/mcpu-bf525.c: Likewise.
+	* gcc.target/bfin/mcpu-bf526.c: Likewise.
+	* gcc.target/bfin/mcpu-bf527.c: Likewise.
+	* gcc.target/bfin/mcpu-bf542.c: Likewise.
+	* gcc.target/bfin/mcpu-bf544.c: Likewise.
+	* gcc.target/bfin/mcpu-bf547.c: Likewise.
+	* gcc.target/bfin/mcpu-bf548.c: Likewise.
+	* gcc.target/bfin/mcpu-bf549.c: Likewise.
+
 2008-09-01  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
 
 	PR fortran/37228
Index: config/bfin/bfin.c
===================================================================
--- config/bfin/bfin.c	(revision 139930)
+++ config/bfin/bfin.c	(working copy)
@@ -114,21 +114,33 @@ struct bfin_cpu
 
 struct bfin_cpu bfin_cpus[] =
 {
+  {"bf522", BFIN_CPU_BF522, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf522", BFIN_CPU_BF522, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf523", BFIN_CPU_BF523, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf523", BFIN_CPU_BF523, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf524", BFIN_CPU_BF524, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf524", BFIN_CPU_BF524, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf525", BFIN_CPU_BF525, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf525", BFIN_CPU_BF525, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf526", BFIN_CPU_BF526, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf526", BFIN_CPU_BF526, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf527", BFIN_CPU_BF527, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf527", BFIN_CPU_BF527, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
@@ -178,6 +190,8 @@ struct bfin_cpu bfin_cpus[] =
    WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf538", BFIN_CPU_BF538, 0x0003,
    WA_SPECULATIVE_LOADS | WA_RETS},
+  {"bf538", BFIN_CPU_BF538, 0x0002,
+   WA_SPECULATIVE_LOADS | WA_RETS},
 
   {"bf539", BFIN_CPU_BF539, 0x0004,
    WA_SPECULATIVE_LOADS | WA_RETS},
@@ -186,18 +200,28 @@ struct bfin_cpu bfin_cpus[] =
   {"bf539", BFIN_CPU_BF539, 0x0002,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf542", BFIN_CPU_BF542, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf542", BFIN_CPU_BF542, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf544", BFIN_CPU_BF544, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf544", BFIN_CPU_BF544, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf547", BFIN_CPU_BF547, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf547", BFIN_CPU_BF547, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf548", BFIN_CPU_BF548, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf548", BFIN_CPU_BF548, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf549", BFIN_CPU_BF549, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf549", BFIN_CPU_BF549, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
Index: testsuite/gcc.target/bfin/mcpu-bf522.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf522.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf522.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
Index: testsuite/gcc.target/bfin/mcpu-bf523.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf523.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf523.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
Index: testsuite/gcc.target/bfin/mcpu-bf542.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf542.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf542.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
Index: testsuite/gcc.target/bfin/mcpu-bf524.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf524.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf524.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
Index: testsuite/gcc.target/bfin/mcpu-bf525.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf525.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf525.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
Index: testsuite/gcc.target/bfin/mcpu-bf544.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf544.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf544.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
Index: testsuite/gcc.target/bfin/mcpu-bf526.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf526.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf526.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
Index: testsuite/gcc.target/bfin/mcpu-bf527.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf527.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf527.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
Index: testsuite/gcc.target/bfin/mcpu-bf547.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf547.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf547.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
Index: testsuite/gcc.target/bfin/mcpu-bf548.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf548.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf548.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
Index: testsuite/gcc.target/bfin/mcpu-bf549.c
===================================================================
--- testsuite/gcc.target/bfin/mcpu-bf549.c	(revision 139886)
+++ testsuite/gcc.target/bfin/mcpu-bf549.c	(working copy)
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED
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