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Vladimir Makarov wrote:There are two types of tying of dying source operand and destination operand. One is for operand that should be the same as the destination (possibly after commutative operand exchange) according the insn constraints. And another one is to decrease register shuffling. The first one has bigger priority (or cost) than the second one because the first type tying removes a real insn.This got me thinking about a long standing poor code problem on the H8 (and likely other processors). Can IRA "tie" a dying source operand to a destination operand when the source & destination operands have different modes?The following patch solves IRA regression on pr36222 and p36246 of gcc testsuite. The analysis of the problem could be found in
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37243
The patch has been bootstrapped sucessfully on x86_64. It also improves SPEC results at least for x86.
2008-08-29 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-opt/37243
* ira-conflicts.c (REG_SUBREG_P, go_through_subreg): New. (process_regs_for_copy): Process subregs. Refine check when cost is taken into account in ira-costs.c. (process_reg_shuffles): Use REG_SUBREG_P. (add_insn_allocno_copies): Ditto. Ignore modes.
* ira-color.c (conflict_allocno_vec): New.
(COST_HOP_DIVISOR): New macro.
(update_copy_costs_1): Use it.
(update_conflict_hard_regno_costs): New function.
(assign_hard_reg): Use it.
(ira_color): Allocate and free conflict_allocno_vec.
This comes up with the zero/sign extension patterns on some targets. The source & destination are required to match, but they have different modes. This case was never handled well by the old allocator resulting in some obviously bad register allocations.Yes, I agree it is important.
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