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[PATCH, testsuite] Fix subreg-related test cases for SPU
- From: "Ulrich Weigand" <uweigand at de dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 15 Jun 2008 17:53:23 +0200 (CEST)
- Subject: [PATCH, testsuite] Fix subreg-related test cases for SPU
Hello,
a small number of test cases make assumptions about the layout of
SImode and DImode values in registers that are not true on the SPU:
We have 16-byte registers, but SImode values reside in bytes 0..3
and DImode values reside in bytes 0..7 of the register. Because
the platform is big-endian, this means simply interpreting a register
holding a DImode value as if it were SImode will get you the high
word (not the low word) of the DImode value.
This patch simply skips those tests on SPU (as some of them are
already skipped on other platforms, e.g. mips64).
Tested on spu-elf with no regressions, fixes the FAILs in the tests.
OK for mainline and 4.3 branch?
Bye,
Ulrich
ChangeLog:
* gcc.c-torture/execute/20030222-1.x: New file.
* gcc.dg/tree-ssa/ssa-fre-3.c: Disable test on SPU.
* gcc.dg/lower-subreg-1.c: Likewise.
Index: gcc/testsuite/gcc.c-torture/execute/20030222-1.x
===================================================================
*** gcc/testsuite/gcc.c-torture/execute/20030222-1.x (revision 0)
--- gcc/testsuite/gcc.c-torture/execute/20030222-1.x (revision 0)
***************
*** 0 ****
--- 1,6 ----
+ if [istarget "spu-*-*"] {
+ # Using inline assembly to convert long long to int is not working quite
+ # right # on the SPU. An extra shift-left-4-byte is needed.
+ return 1
+ }
+ return 0
Index: gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
===================================================================
*** gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c (revision 136680)
--- gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c (working copy)
***************
*** 5,11 ****
When the condition is true, we distribute "(int) (a + b)" as
"(int) a + (int) b", otherwise we keep the original. */
! /* { dg-do compile { target { ! mips64 } } } */
/* { dg-options "-O -fwrapv -fdump-tree-fre-details" } */
/* From PR14844. */
--- 5,11 ----
When the condition is true, we distribute "(int) (a + b)" as
"(int) a + (int) b", otherwise we keep the original. */
! /* { dg-do compile { target { { ! mips64 } && { ! spu-*-* } } } } */
/* { dg-options "-O -fwrapv -fdump-tree-fre-details" } */
/* From PR14844. */
Index: gcc/testsuite/gcc.dg/lower-subreg-1.c
===================================================================
*** gcc/testsuite/gcc.dg/lower-subreg-1.c (revision 136680)
--- gcc/testsuite/gcc.dg/lower-subreg-1.c (working copy)
***************
*** 1,4 ****
! /* { dg-do compile { target { { ! mips64 } && { ! ia64-*-* } } } } */
/* { dg-options "-O -fdump-rtl-subreg" } */
/* { dg-require-effective-target ilp32 } */
--- 1,4 ----
! /* { dg-do compile { target { { { ! mips64 } && { ! ia64-*-* } } && { ! spu-*-* } } } } */
/* { dg-options "-O -fdump-rtl-subreg" } */
/* { dg-require-effective-target ilp32 } */
--
Dr. Ulrich Weigand
GNU Toolchain for Linux on System z and Cell BE
Ulrich.Weigand@de.ibm.com