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[ira] avr support and small fix in the reload
- From: Vladimir Makarov <vmakarov at redhat dot com>
- To: gcc-patches <gcc-patches at gcc dot gnu dot org>
- Cc: Andy H <hutchinsonandy at aim dot com>
- Date: Thu, 29 May 2008 14:22:41 -0400
- Subject: [ira] avr support and small fix in the reload
Here, this is Andy Hutchinson's patch bringing IRA for AVR and a small
fix in choosing spill register important for AVR and may be for other
platforms.
2008-05-29 Andy Hutchinson <hutchinsonandy@aim.com>
* config/avr/avr.h (IRA_COVER_CLASSES): New macro
* reload1.c (find_reg): Process registers in register allocation
order.
Index: config/avr/avr.h
===================================================================
--- config/avr/avr.h (revision 136176)
+++ config/avr/avr.h (working copy)
@@ -291,6 +291,19 @@ enum reg_class {
#define REGNO_REG_CLASS(R) avr_regno_reg_class(R)
+/* The following macro defines cover classes for Integrated Register
+ Allocator. Cover classes is a set of non-intersected register
+ classes covering all hard registers used for register allocation
+ purpose. Any move between two registers of a cover class should be
+ cheaper than load or store of the registers. The macro value is
+ array of register classes with LIM_REG_CLASSES used as the end
+ marker. */
+
+#define IRA_COVER_CLASSES \
+{ \
+ GENERAL_REGS, LIM_REG_CLASSES \
+}
+
#define BASE_REG_CLASS (reload_completed ? BASE_POINTER_REGS : POINTER_REGS)
#define INDEX_REG_CLASS NO_REGS
Index: reload1.c
===================================================================
--- reload1.c (revision 136176)
+++ reload1.c (working copy)
@@ -1869,7 +1869,11 @@ find_reg (struct insn_chain *chain, int
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
+#ifdef REG_ALLOC_ORDER
+ unsigned int regno = reg_alloc_order[i];
+#else
unsigned int regno = i;
+#endif
if (! TEST_HARD_REG_BIT (not_usable, regno)
&& ! TEST_HARD_REG_BIT (used_by_other_reload, regno)