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mips64 xlr processor support
- From: Sandip Matte <sandip at rmicorp dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 27 May 2008 18:45:20 +0530
- Subject: mips64 xlr processor support
Hello,
This patch adds support for RMI Corp's mips64 xlr processor.
New option -march=xlr and -mtune=xlr are added for xlr
processor. Tested mips64-unknown-linux-gnu with -march=xlr and
-mtune=xlr.
Thanks,
Sandip
2008-05-27 Sandip Matte <sandip@rmicorp.com>
* gcc/config/mips/xlr.md: New file for defining xlr processor automaton.
* gcc/config.gcc: Add new targets mipsisa64xlr-*-elf* and
mipsisa64xlrel-*-elf*
* gcc/config/mips/mips.md: new architecture xlr is added.
* gcc/config/mips/mips.h: Add definition for xlr processor.
* gcc/config/mips/mips.c: Add xlr processor entry in
mips_cpu_info_table and mips_rtx_cost_data.
diff -Naur gcc-4.2.4.orig/gcc/config/mips/mips.c gcc-4.2.4/gcc/config/mips/mips.c
--- gcc-4.2.4.orig/gcc/config/mips/mips.c 2008-05-27 14:37:44.001093000 +0530
+++ gcc-4.2.4/gcc/config/mips/mips.c 2008-05-27 14:42:47.001394000 +0530
@@ -759,6 +759,7 @@
{ "sb1", PROCESSOR_SB1, 64 },
{ "sb1a", PROCESSOR_SB1A, 64 },
{ "sr71000", PROCESSOR_SR71000, 64 },
+ { "xlr", PROCESSOR_XLR, 64 },
/* End marker */
{ 0, 0, 0 }
@@ -1045,6 +1046,21 @@
{ /* SR71000 */
DEFAULT_COSTS
},
+ { /* XLR */
+ /* Need to replace first five with the costs of calling the appropriate
+ libgcc routine.*/
+ COSTS_N_INSNS (256), /* fp_add */
+ COSTS_N_INSNS (256), /* fp_mult_sf */
+ COSTS_N_INSNS (256), /* fp_mult_df */
+ COSTS_N_INSNS (256), /* fp_div_sf */
+ COSTS_N_INSNS (256), /* fp_div_df */
+ COSTS_N_INSNS (8), /* int_mult_si */
+ COSTS_N_INSNS (8), /* int_mult_di */
+ COSTS_N_INSNS (72), /* int_div_si */
+ COSTS_N_INSNS (72), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
};
diff -Naur gcc-4.2.4.orig/gcc/config/mips/mips.h gcc-4.2.4/gcc/config/mips/mips.h
--- gcc-4.2.4.orig/gcc/config/mips/mips.h 2008-05-27 14:37:44.001351000 +0530
+++ gcc-4.2.4/gcc/config/mips/mips.h 2008-05-27 14:42:47.001476000 +0530
@@ -59,6 +59,7 @@
PROCESSOR_SB1,
PROCESSOR_SB1A,
PROCESSOR_SR71000,
+ PROCESSOR_XLR,
PROCESSOR_MAX
};
diff -Naur gcc-4.2.4.orig/gcc/config/mips/mips.md gcc-4.2.4/gcc/config/mips/mips.md
--- gcc-4.2.4.orig/gcc/config/mips/mips.md 2008-05-27 14:37:45.000101000 +0530
+++ gcc-4.2.4/gcc/config/mips/mips.md 2008-05-27 14:42:47.001602000 +0530
@@ -343,7 +343,7 @@
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
- "r3000,4kc,4kp,5kc,5kf,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
+ "r3000,4kc,4kp,5kc,5kf,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
@@ -600,6 +600,7 @@
(include "9000.md")
(include "sb1.md")
(include "sr71k.md")
+(include "xlr.md")
(include "generic.md")
;;
diff -Naur gcc-4.2.4.orig/gcc/config/mips/xlr.md gcc-4.2.4/gcc/config/mips/xlr.md
--- gcc-4.2.4.orig/gcc/config/mips/xlr.md 1970-01-01 05:30:00.000000000 +0530
+++ gcc-4.2.4/gcc/config/mips/xlr.md 2008-05-27 14:42:47.001864000 +0530
@@ -0,0 +1,87 @@
+;; Software Code Disclaimer
+;; xlr.md Machine Description for the RMI XLR Microprocessor
+;; Copyright © 2008 Raza Microelectronics, Inc. "RMI")
+;;
+;; This program is free software. You may use it, redistribute it
+;; and/or modify it under the terms of the GNU General Public License
+;; as published by the Free Software Foundation; either version two
+;; of the License or (at your option) any later version.
+;;
+;; This program is distributed in the hope that you will find it
+;; useful. Notwithstanding the foregoing, you understand and agree
+;; that this program is provided by RMI "as is," and without any
+;; warranties, whether express, implied or statutory, including without
+;; limitation any implied warranty of non-infringement, merchantability
+;; or fitness for a particular purpose. In no event will RMI be liable
+;; for any loss of data, lost profits, cost of procurement of substitute
+;; technology or services or for any direct, indirect, incidental,
+;; consequential or special damages arising from the use of this program,
+;; however caused. Your unconditional agreement to these terms and
+;; conditions is an express condition to, and shall be deemed to occur
+;; upon, your use, redistribution and/or modification of this program.
+;;
+;; See the GNU General Public License for more details.
+
+
+(define_automaton "xlr_main,xlr_muldiv")
+
+;; definitions for xlr_main automaton
+(define_cpu_unit "xlr_main_pipe" "xlr_main")
+
+(define_insn_reservation "ir_xlr_alu_slt" 2
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "slt"))
+ "xlr_main_pipe")
+
+;; integer arithmetic instructions
+(define_insn_reservation "ir_xlr_alu" 1
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "arith,shift,clz,const,unknown,multi,nop,trap"))
+ "xlr_main_pipe")
+
+;; integer arithmetic instructions
+(define_insn_reservation "ir_xlr_condmove" 2
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "condmove"))
+ "xlr_main_pipe")
+
+;; load/store instructions
+(define_insn_reservation "ir_xlr_load" 4
+ (and (eq_attr "cpu" "xlr") (eq_attr "type" "load"))
+ "xlr_main_pipe")
+
+(define_insn_reservation "ir_xlr_store" 1
+ (and (eq_attr "cpu" "xlr") (eq_attr "type" "store"))
+ "xlr_main_pipe")
+
+(define_insn_reservation "ir_xlr_prefetch_x" 1
+ (and (eq_attr "cpu" "xlr")
+ (eq_attr "type" "prefetch,prefetchx"))
+ "sb1_ls1")
+
+(define_insn_reservation "ir_xlr_branch" 1
+ (and (eq_attr "cpu" "xlr") (eq_attr "type" "branch,jump,call"))
+ "xlr_main_pipe")
+
+;; coprocessor move instructions
+(define_insn_reservation "ir_xlr_xfer" 2
+ (and (eq_attr "cpu" "xlr") (eq_attr "type" "xfer"))
+ "xlr_main_pipe")
+
+(define_bypass 5 "ir_xlr_xfer" "ir_xlr_xfer")
+
+;; definitions for the xlr_muldiv automaton
+(define_cpu_unit "xlr_imuldiv_nopipe" "xlr_muldiv")
+
+(define_insn_reservation "ir_xlr_imul" 8
+ (and (eq_attr "cpu" "xlr") (eq_attr "type" "imul,imul3,imadd"))
+ "xlr_main_pipe,xlr_imuldiv_nopipe*6")
+
+(define_insn_reservation "ir_xlr_div" 68
+ (and (eq_attr "cpu" "xlr") (eq_attr "type" "idiv"))
+ "xlr_main_pipe,xlr_imuldiv_nopipe*67")
+
+(define_insn_reservation "xlr_hilo" 2
+ (and (eq_attr "cpu" "xlr") (eq_attr "type" "mfhilo,mthilo"))
+ "xlr_imuldiv_nopipe")
+
diff -Naur gcc-4.2.4.orig/gcc/config.gcc gcc-4.2.4/gcc/config.gcc
--- gcc-4.2.4.orig/gcc/config.gcc 2008-05-27 14:31:12.000051000 +0530
+++ gcc-4.2.4/gcc/config.gcc 2008-05-27 14:42:48.000440000 +0530
@@ -1609,6 +1609,14 @@
tm_defines="${tm_defines} MIPS_ISA_DEFAULT=64 MIPS_CPU_STRING_DEFAULT=\\\"sb1\\\" MIPS_ABI_DEFAULT=ABI_O64"
use_fixproto=yes
;;
+mipsisa64xlr-*-elf* | mipsisa64xlrel-*-elf*)
+ tm_defines="MIPS_ISA_DEFAULT=64 MIPS_CPU_STRING_DEFAULT=\\\"xlr\\\" MIPS_ABI_DEFAULT=ABI_O64"
+ tm_file="elfos.h ${tm_file} mips/elf.h"
+ tmake_file=mips/t-isa3264
+ extra_parts="crtbeginT.o"
+ target_cpu_default="MASK_64BIT | MASK_SOFT_FLOAT"
+ use_fixproto=yes
+ ;;
mips-*-elf* | mipsel-*-elf*)
tm_file="elfos.h ${tm_file} mips/elf.h"
tmake_file=mips/t-elf