Re: PATCH: Break up ix86_expand_vector_init_general

["H.J. Lu" <hjl dot tools at gmail dot com>]

Hi,

I missed the following change:
Index: gcc/config/i386/i386.c
===================================================================
--- gcc/config/i386/i386.c      (revision 2634)
+++ gcc/config/i386/i386.c      (working copy)
@@ -23848,7 +23848,7 @@ ix86_expand_vector_init_concat (enum mac
                                rtx target, rtx *ops, int n)
 {
   enum machine_mode cmode, hmode = VOIDmode;
-  rtx first[8], second[4];
+  rtx first[4], second[2];
   rtvec v;
   int i, j;

@@ -24054,7 +24054,7 @@ static void
 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
                                 rtx target, rtx vals)
 {
-  rtx ops[32], op0, op1;
+  rtx ops[16];
   enum machine_mode half_mode = VOIDmode;
   int n, i;


H.J.


On Mon, May 19, 2008 at 11:52 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Mon, May 19, 2008 at 11:25 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
>> H.J. Lu wrote:
>>
>>> This patch is from AVX branch. It breaks up
>>> ix86_expand_vector_init_general
>>> into 3 functions so the they can be reused to support 256bit vectors. The
>>> current x86 backend have 256bit vector types, like V8SImode, V8SFmode, ...
>>> But there are no patterns to generate any instructions for them. The
>>> 256bit
>>> parts of those functions will only be called when AVX support is added to
>>> mainline. Since 256bit vector parts don't cause any regressions on
>>> Linux/Intel64, I didn't take them out. I can remove them if necessary.
>>> Also the code
>>>
>>
>> Please commit only non-AVX part. I think that introducing dead code that
>> will support future patches is not appropriate, since we will lost track
>> what is already committed. I would rather see future AVX patch packed
>> together with its md patterns and supporting functionality.
>>
>>> 2008-05-19  H.J. Lu  <hongjiu.lu@intel.com>
>>>
>>>        * config/i386/i386.c (ix86_expand_vector_init_concat): New.
>>>        (ix86_expand_vector_init_interleave): Likewise.
>>>        (ix86_expand_vector_init_general): Use them.  Assert word_mode
>>>        == SImode when n_words == 4.
>>>
>>
>>
>> This is OK for mainline, but please without AVX support code.
>>
>>
>
> Here is the change I am checking in with the ChangeLog entry above.
>
> Thanks.
>
>
> H.J.
>