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Re: Update SSE5 vector multiplication, shift, rotate, take 2
- From: "Andrew Pinski" <pinskia at gmail dot com>
- To: "Michael Meissner" <michael dot meissner at amd dot com>, gcc-patches at gcc dot gnu dot org, dwarak dot rajagopal at amd dot com, christophe dot harle at amd dot com, hongjiu dot lu at intel dot com, ubizjak at gmail dot com
- Date: Thu, 8 May 2008 18:03:14 -0700
- Subject: Re: Update SSE5 vector multiplication, shift, rotate, take 2
- References: <20080417185036.GA15776@mmeissner-gold.amd.com> <20080508212421.GA4882@mmeissner-gold.amd.com>
On Thu, May 8, 2008 at 2:24 PM, Michael Meissner
<michael.meissner@amd.com> wrote:
> BTW, the SPU current without patches aborts if you try to code up a rotate,
> just like the current x86 with -msse5 does without my patches. With my
> patches, it looks like it generates a vector rotate:
I removed the assert and it worked, the assert was added to make sure
we don't get partial modes but it really should be also checking if it
is not a VECTOR_TYPE. This assert was added for PR 34971.
Thanks,
Andrew Pinski