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[RFA] PowerPC e500mc core support
- From: Edmar Wienskoski-RA8797 <edmar at freescale dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Mon, 05 May 2008 13:48:08 -0500
- Subject: [RFA] PowerPC e500mc core support
Freescale would like to contribute this patch to gcc. It creates a
scheduler
and proper default flags for the e500mc core.
Could some PowerPC maintainer review and commit the patch ?
Regards,
Edmar
2008-04-30 Edmar Wienskoski <edmar@freescale.com>
* config.gcc (powerpc*-*-*): Add new core e500mc.
* config/rs6000/e500mc.md: New file.
* config/rs6000/rs6000.c (processor_costs): Add new costs for
e500mc.
(rs6000_override_options): Add e500mc case to
processor_target_table. Add isel instruction to e500mc. Initialize
rs6000_cost for e500mc.
(rs6000_issue_rate): Set issue rate for e500mc.
* config/rs6000/rs6000.h (processor_type): Add
PROCESSOR_PPCE500MC.
(ASM_CPU_SPEC): Add e500mc.
* config/rs6000/rs6000.md (define_attr "cpu"): Add ppce500mc.
Include e500mc.md.
* doc/invoke.texi: Add e500mc to list of cpus.
Index: gcc/gcc/doc/invoke.texi
===================================================================
--- gcc/gcc/doc/invoke.texi (revision 134824)
+++ gcc/gcc/doc/invoke.texi (working copy)
@@ -12949,11 +12949,11 @@
@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
@samp{860}, @samp{970}, @samp{8540}, @samp{e300c2}, @samp{e300c3},
-@samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{power},
-@samp{power2}, @samp{power3}, @samp{power4}, @samp{power5},
-@samp{power5+}, @samp{power6}, @samp{power6x}, @samp{common},
-@samp{powerpc}, @samp{powerpc64}, @samp{rios}, @samp{rios1},
-@samp{rios2}, @samp{rsc}, and @samp{rs64}.
+@samp{e500mc}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
+@samp{power}, @samp{power2}, @samp{power3}, @samp{power4},
+@samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x},
+@samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
+@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mcpu=common} selects a completely generic processor. Code
generated under this option will run on any POWER or PowerPC processor.
Index: gcc/gcc/config.gcc
===================================================================
--- gcc/gcc/config.gcc (revision 134824)
+++ gcc/gcc/config.gcc (working copy)
@@ -3149,8 +3149,9 @@
| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
| 601 | 602 | 603 | 603e | ec603e | 604 \
- | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
- | 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
+ | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
+ | e300c[23] | 854[08] | e500mc \
+ | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
# OK
;;
*)
Index: gcc/gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/gcc/config/rs6000/rs6000.c (revision 134824)
+++ gcc/gcc/config/rs6000/rs6000.c (working copy)
@@ -694,6 +694,25 @@
1, /* prefetch streams /*/
};
+/* Instruction costs on PPCE500MC processors. */
+static const
+struct processor_costs ppce500mc_cost = {
+ COSTS_N_INSNS (4), /* mulsi */
+ COSTS_N_INSNS (4), /* mulsi_const */
+ COSTS_N_INSNS (4), /* mulsi_const9 */
+ COSTS_N_INSNS (4), /* muldi */
+ COSTS_N_INSNS (14), /* divsi */
+ COSTS_N_INSNS (14), /* divdi */
+ COSTS_N_INSNS (8), /* fp */
+ COSTS_N_INSNS (10), /* dmul */
+ COSTS_N_INSNS (36), /* sdiv */
+ COSTS_N_INSNS (66), /* ddiv */
+ 64, /* cache line size */
+ 32, /* l1 cache */
+ 128, /* l2 cache */
+ 1, /* prefetch streams /*/
+};
+
/* Instruction costs on POWER4 and POWER5 processors. */
static const
struct processor_costs power4_cost = {
@@ -1446,6 +1465,7 @@
{"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
{"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
+ {"e500mc", PROCESSOR_PPCE500MC, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
{"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"970", PROCESSOR_POWER4,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
@@ -1560,6 +1580,9 @@
error ("Spe not supported in this target");
}
+ if (rs6000_cpu == PROCESSOR_PPCE500MC)
+ rs6000_isel = 1;
+
/* If we are optimizing big endian systems for space, use the load/store
multiple and string instructions. */
if (BYTES_BIG_ENDIAN && optimize_size)
@@ -1884,6 +1907,10 @@
rs6000_cost = &ppce300c2c3_cost;
break;
+ case PROCESSOR_PPCE500MC:
+ rs6000_cost = &ppce500mc_cost;
+ break;
+
case PROCESSOR_POWER4:
case PROCESSOR_POWER5:
rs6000_cost = &power4_cost;
@@ -18642,6 +18669,7 @@
case CPU_CELL:
case CPU_PPCE300C2:
case CPU_PPCE300C3:
+ case CPU_PPCE500MC:
return 2;
case CPU_RIOS2:
case CPU_PPC604:
Index: gcc/gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/gcc/config/rs6000/rs6000.h (revision 134824)
+++ gcc/gcc/config/rs6000/rs6000.h (working copy)
@@ -131,6 +131,7 @@
%{mcpu=8548: -me500} \
%{mcpu=e300c2: -me300} \
%{mcpu=e300c3: -me300} \
+%{mcpu=e500mc: -me500mc} \
%{maltivec: -maltivec} \
-many"
@@ -280,6 +281,7 @@
PROCESSOR_PPC8540,
PROCESSOR_PPCE300C2,
PROCESSOR_PPCE300C3,
+ PROCESSOR_PPCE500MC,
PROCESSOR_POWER4,
PROCESSOR_POWER5,
PROCESSOR_POWER6,
Index: gcc/gcc/config/rs6000/e500mc.md
===================================================================
--- gcc/gcc/config/rs6000/e500mc.md (revision 0)
+++ gcc/gcc/config/rs6000/e500mc.md (revision 0)
@@ -0,0 +1,198 @@
+;; Pipeline description for Motorola PowerPC e500mc core.
+;; Copyright (C) 2008 Free Software Foundation, Inc.
+;; Contributed by Edmar Wienskoski (edmar@freescale.com)
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+;;
+;; e500mc 32-bit SU(2), LSU, FPU, BPU
+;; Max issue 3 insns/clock cycle (includes 1 branch)
+;; FP is half clocked, other isntructions has similar timing as in the e500
+
+(define_automaton "e500mc_most,e500mc_long,e500mc_retire")
+(define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most")
+(define_cpu_unit "e500mc_issue_0,e500mc_issue_1" "e500mc_most")
+(define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire")
+
+;; SU:
+(define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most")
+
+;; MU
+(define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most")
+(define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most")
+
+;; non-pipelined division.
+(define_cpu_unit "e500mc_mu_div" "e500mc_long")
+
+;; LSU
+(define_cpu_unit "e500mc_lsu" "e500mc_most")
+
+;; FPU:
+(define_cpu_unit "e500mc_fpu" "e500mc_most")
+
+;; Branch unit:
+(define_cpu_unit "e500mc_bu" "e500mc_most")
+
+;; The following units are used to make automata deterministic
+(define_cpu_unit "present_e500mc_decode_0" "e500mc_most")
+(define_cpu_unit "present_e500mc_issue_0" "e500mc_most")
+(define_cpu_unit "present_e500mc_retire_0" "e500mc_retire")
+(define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most")
+
+;; The following sets to make automata deterministic when option ndfa is used.
+(presence_set "present_e500mc_decode_0" "e500mc_decode_0")
+(presence_set "present_e500mc_issue_0" "e500mc_issue_0")
+(presence_set "present_e500mc_retire_0" "e500mc_retire_0")
+(presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0")
+
+;; Some useful abbreviations.
+(define_reservation "e500mc_decode"
+ "e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0")
+(define_reservation "e500mc_issue"
+ "e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0")
+(define_reservation "e500mc_retire"
+ "e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0")
+(define_reservation "e500mc_su_stage0"
+ "e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0")
+
+;; Simple SU insns
+(define_insn_reservation "e500mc_su" 1
+ (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
+ delayed_compare,var_delayed_compare,fast_compare,\
+ shift,trap,var_shift_rotate,cntlz,exts")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
+
+(define_insn_reservation "e500mc_two" 1
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
+ e500mc_issue+e500mc_su_stage0+e500mc_retire")
+
+(define_insn_reservation "e500mc_three" 1
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
+ e500mc_issue+e500mc_su_stage0+e500mc_retire,\
+ e500mc_issue+e500mc_su_stage0+e500mc_retire")
+
+;; Multiply
+(define_insn_reservation "e500mc_multiply" 4
+ (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
+ e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
+
+;; Divide. We use the average latency time here.
+(define_insn_reservation "e500mc_divide" 14
+ (and (eq_attr "type" "idiv")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\
+ e500mc_mu_div*13")
+
+;; Branch
+(define_insn_reservation "e500mc_branch" 1
+ (and (eq_attr "type" "jmpreg,branch,isync")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_bu,e500mc_retire")
+
+;; CR logical
+(define_insn_reservation "e500mc_cr_logical" 1
+ (and (eq_attr "type" "cr_logical,delayed_cr")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_bu,e500mc_retire")
+
+;; Mfcr
+(define_insn_reservation "e500mc_mfcr" 1
+ (and (eq_attr "type" "mfcr")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
+
+;; Mtcrf
+(define_insn_reservation "e500mc_mtcrf" 1
+ (and (eq_attr "type" "mtcr")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
+
+;; Mtjmpr
+(define_insn_reservation "e500mc_mtjmpr" 1
+ (and (eq_attr "type" "mtjmpr,mfjmpr")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
+
+;; Brinc
+(define_insn_reservation "e500mc_brinc" 1
+ (and (eq_attr "type" "brinc")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
+
+;; Loads
+(define_insn_reservation "e500mc_load" 3
+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
+ load_l,sync")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
+
+(define_insn_reservation "e500mc_fpload" 4
+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
+
+;; Stores.
+(define_insn_reservation "e500mc_store" 3
+ (and (eq_attr "type" "store,store_ux,store_u,store_c")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
+
+(define_insn_reservation "e500mc_fpstore" 3
+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
+
+;; Simple FP
+(define_insn_reservation "e500mc_simple_float" 8
+ (and (eq_attr "type" "fpsimple")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
+
+;; FP
+(define_insn_reservation "e500mc_float" 8
+ (and (eq_attr "type" "fp")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
+
+(define_insn_reservation "e500mc_fpcompare" 8
+ (and (eq_attr "type" "fpcompare")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
+
+;; The followig ignores the retire unit to avoid a large automata
+
+(define_insn_reservation "e500mc_dmul" 10
+ (and (eq_attr "type" "dmul")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_fpu")
+
+;; FP divides are not pipelined
+(define_insn_reservation "e500mc_sdiv" 36
+ (and (eq_attr "type" "sdiv")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35")
+
+(define_insn_reservation "e500mc_ddiv" 66
+ (and (eq_attr "type" "ddiv")
+ (eq_attr "cpu" "ppce500mc"))
+ "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65")
Index: gcc/gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/gcc/config/rs6000/rs6000.md (revision 134824)
+++ gcc/gcc/config/rs6000/rs6000.md (working copy)
@@ -133,7 +133,7 @@
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5,power6,cell"
+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell"
(const (symbol_ref "rs6000_cpu_attr")))
@@ -167,6 +167,7 @@
(include "7450.md")
(include "8540.md")
(include "e300c2c3.md")
+(include "e500mc.md")
(include "power4.md")
(include "power5.md")
(include "power6.md")