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IRA for MIPS testing, anyone?
- From: "Steven Bosscher" <stevenb dot gcc at gmail dot com>
- To: "Mark Mitchell" <mark at codesourcery dot com>
- Cc: "Vladimir Makarov" <vmakarov at redhat dot com>, "Kenneth Zadeck" <zadeck at naturalbridge dot com>, gcc-patches <gcc-patches at gcc dot gnu dot org>, "Richard Sandiford" <rsandifo at nildram dot co dot uk>, "Eric Botcazou" <ebotcazou at libertysurf dot fr>, "Bergner, Peter" <bergner at vnet dot ibm dot com>, "Bonzini, Paolo" <bonzini at gnu dot org>, "Park, Seongbae" <seongbae dot park at gmail dot com>
- Date: Wed, 23 Apr 2008 22:17:33 +0200
- Subject: IRA for MIPS testing, anyone?
Taling about IRA...
Any MIPS folks who want to try the attached patch? I've had it in my
local copy of the IRA branch for weeks now, but I can't seem to find
the time to test whether it works.
Gr.
Steven
* config/mips/mips.h (REG_CLASS_CONTENTS): Fix contents of ALL_REGS.
(IRA_COVER_CLASSES): Define.
Index: config/mips/mips.h
===================================================================
--- config/mips/mips.h (revision 133981)
+++ config/mips/mips.h (working copy)
@@ -1757,10 +1757,24 @@
{ 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
- { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
+ { 0xffffffff, 0xffffffff, 0xffff07fb, 0xffffffff, 0xffffffff, 0x003fffff } /* all registers */ \
}
+/* The following macro defines cover classes for Integrated Register
+ Allocator. Cover classes is a set of non-intersected register
+ classes covering all hard registers used for register allocation
+ purpose. Any move between two registers of a cover class should be
+ cheaper than load or store of the registers. The macro value is
+ array of register classes with LIM_REG_CLASSES used as the end
+ marker. */
+#define IRA_COVER_CLASSES \
+{ \
+ PIC_FN_ADDR_REG, LEA_REGS, FP_REGS, MD_REGS, \
+ COP0_REGS, COP2_REGS, COP3_REGS, \
+ ST_REGS, DSP_ACC_REGS, LIM_REG_CLASSES \
+}
+
/* A C expression whose value is a register class containing hard
register REGNO. In general there is more that one such class;
choose a class which is "minimal", meaning that no smaller class