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Re: PATCH: Enable Intel AES/CLMUL
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Thu, 03 Apr 2008 19:41:49 +0200
- Subject: Re: PATCH: Enable Intel AES/CLMUL
Hello!
* config/i386/i386.c (OPTION_MASK_ISA_AES_SET): New.
(OPTION_MASK_ISA_CLMUL_SET): Likewise.
(OPTION_MASK_ISA_AES_UNSET): Likewise.
(OPTION_MASK_ISA_CLMUL_UNSET): Likewise.
(OPTION_MASK_ISA_SSE4_2_UNSET): Add OPTION_MASK_ISA_AES_UNSET
and OPTION_MASK_ISA_CLMUL_UNSET.
I don't think that MASK_ISA is correct approach here, since MASK_ISA is
reserved for different SSE levels that siwtch on or off whole pack of
instructions. Perhaps we should do with:
i386.h:
#define TARGET_CLMUL x86_aes
where
i386.opt:
maes
Target Report RejectNegative Var(x86_aes)
We can even #define TARGET_CLMUL (TARGET_SSE4_2 && x86_aes), depending
on how we want to enable generation of AES instructions. Please also
note, that we will use PTA_* flags in future for certain targets and we
can switch this flag depending on target features. So:
gcc -msse -maes
or
gcc -mfancy_future_target
will both switch AES instruction supports on.
Regarding the tests, all new *intrin.h should also be added to
gcc.target/i386/sse-[13,14] to check that intrinsics compile with and
without optimization (I would also recommend to add the header to
g++.dg/other/i386-3.C)
Uros.