Hi,
movti may generate SSE vector move for TDmode. When TDmode is
aligned at 1 byte, movti generates aligned load on unaligned
memory. This patch adds a new predicate and uses it to check
misaligned operand to generate unaligned move if needed.
H.J.
----
2008-03-30 H.J. Lu <hongjiu.lu@intel.com>
PR target/32000
* config/i386/i386.md (*movti_internal): Emit unaligned SSE
load/store if memory is unaligned.
(*movti_rex64): Likewise.
* config/i386/predicates.md (misaligned_operand): New.
2008-03-30 H.J. Lu <hongjiu.lu@intel.com>
PR target/32000
* gcc.target/i386/pr32000-1.c: New.
* gcc.target/i386/pr32000-2.c: Likewise.
* gcc.target/i386/pr32000-3.c: Likewise.
* gcc.target/i386/pr32000-4.c: Likewise.
* gcc.target/i386/pr32000-5.c: Likewise.
* gcc.target/i386/pr32000-6.c: Likewise.
--- gcc/config/i386/i386.md.td 2008-03-30 10:07:59.000000000 -0700
+++ gcc/config/i386/i386.md 2008-03-30 10:07:59.000000000 -0700
@@ -2387,10 +2387,23 @@
return "pxor\t%0, %0";
case 1:
case 2:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
+ /* TDmode values are passed as TImode on the stack. Moving them
+ to stack may result in unaligned memory access. */
+ if (misaligned_operand (operands[0], TImode)
+ || misaligned_operand (operands[1], TImode))
+ {
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "movups\t{%1, %0|%0, %1}";
+ else
+ return "movdqu\t{%1, %0|%0, %1}";
+ }
else
- return "movdqa\t{%1, %0|%0, %1}";
+ {
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "movaps\t{%1, %0|%0, %1}";
+ else
+ return "movdqa\t{%1, %0|%0, %1}";
+ }
default:
gcc_unreachable ();
}