[PATCH,rs6000] PR target/35373: Fix mainline bootstrap and regression problems

[Peter Bergner <bergner at vnet dot ibm dot com>]

This patches fixes some additional fallout from Joseph's patch:

    http://gcc.gnu.org/ml/gcc-patches/2007-09/msg01959.html

similar to that found by Nathan:

    http://gcc.gnu.org/ml/gcc-patches/2008-01/msg00249.html

The two patches hunks fix two different problems caused by the new gcc_assert.
The second hunk fixes the bootstrap issue reported in PR35373, but disallowing
reg+reg addressing for TFmode and TDmode types for the same reasons Nathan
stated in his patch.

The first hunk fixes a testsuite regression (vect-64.c) caused by the new
gcc_assert that is exposed after fixing the bootstrap.  In this particular
case, memory_address() calls LEGITIMIZE_ADDRESS to fixup a reg+const address
where the constant is too big.  In rs6000_legitimize_address, we detect
the reg+const address with the too large constant and fix it up and return
another reg+const address.  We then execute Joseph's new gcc_assert where we
verify that the address is valid.  The problem here is that we're dealing
with V4SImode for which only reg+reg addressing is valid.  The fix is to
just disallow fixing up of reg+large_const addresses for Altivec modes.

This has bootstrapped on powerpc64-linux.  For regression testing, I used
the revision created with Joseph's patch along with the previous revision
(since nothing after that boostrapped) and found no regressions.

Is this ok for mainline?

Peter

	PR target/35373
	* config/rs6000/rs6000.c (rs6000_legitimize_address): Don't generate
	reg+const addressing for Altivec modes.  Don't generate reg+reg
	addressing for TFmode or TDmode quantities.

Index: config/rs6000/rs6000.c
===================================================================
--- config/rs6000/rs6000.c	(revision 132951)
+++ config/rs6000/rs6000.c	(working copy)
@@ -3616,6 +3616,7 @@ rs6000_legitimize_address (rtx x, rtx ol
       && GET_CODE (XEXP (x, 1)) == CONST_INT
       && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000
       && !(SPE_VECTOR_MODE (mode)
+	   || ALTIVEC_VECTOR_MODE (mode)
 	   || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
 				      || mode == DImode))))
     {
@@ -3633,11 +3634,12 @@ rs6000_legitimize_address (rtx x, rtx ol
 	   && GET_MODE_NUNITS (mode) == 1
 	   && ((TARGET_HARD_FLOAT && TARGET_FPRS)
 	       || TARGET_POWERPC64
-	       || (((mode != DImode && mode != DFmode && mode != DDmode)
-		    || TARGET_E500_DOUBLE)
-		   && mode != TFmode && mode != TDmode))
+	       || ((mode != DImode && mode != DFmode && mode != DDmode)
+		   || TARGET_E500_DOUBLE))
 	   && (TARGET_POWERPC64 || mode != DImode)
-	   && mode != TImode)
+	   && mode != TImode
+	   && mode != TFmode
+	   && mode != TDmode)
     {
       return gen_rtx_PLUS (Pmode, XEXP (x, 0),
 			   force_reg (Pmode, force_operand (XEXP (x, 1), 0)));