[committed] Sync code with pending fix for PR34900

[Richard Sandiford <rsandifo at nildram dot co dot uk>]

PR34900 is a 4.2 build failure for mips64vrel-elf.  It is really the
same as PR 31388, which was fixed on mainline with:

2007-04-01  Richard Sandiford  <richard@codesourcery.com>

	PR target/31388
	* config/mips/mips.md (load_const_gp): New insn.
	* config/mips/mips.c (mips_split_symbol): Avoid using or creating
	the MIPS16 GP pseudo register if no_new_pseudos.
	(mips16_gp_pseudo_reg): Use gen_load_const_gp.

However, while backporting that patch, I noticed that it had a rather
obvious flaw: the new const had no mode.  I fixed that in the backport,
and although I don't know that the original patch causes any specific
failure, I thought it was safer to fix the 4.3 sources in the same way.
Not doing so might introduce a 4.2.4->4.3 regression.

Tested on mipsisa64-elfoabi and applied.  I'll apply the 4.2 patch
after 4.2.3 is released.

Richard


gcc/
	PR target/34900
	* config/mips/mips.c (gen_load_const_gp): New function, taking a
	comment from...
	(mips16_gp_pseudo_reg): ...here.
	* config/mips/mips.md (load_const_gp): Replace with...
	(load_const_gp_<mode>): ...this :P-based insn.

Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c	2008-01-30 13:03:00.000000000 +0000
+++ gcc/config/mips/mips.c	2008-01-30 13:07:39.000000000 +0000
@@ -2161,6 +2161,18 @@ mips_emit_call_insn (rtx pattern, bool l
   return insn;
 }
 
+/* Return an instruction that copies $gp into register REG.  We want
+   GCC to treat the register's value as constant, so that its value
+   can be rematerialized on demand.  */
+
+static rtx
+gen_load_const_gp (rtx reg)
+{
+  return (Pmode == SImode
+	  ? gen_load_const_gp_si (reg)
+	  : gen_load_const_gp_di (reg));
+}
+
 /* Return a pseudo register that contains the value of $gp throughout
    the current function.  Such registers are needed by MIPS16 functions,
    for which $gp itself is not a valid base register or addition operand.  */
@@ -2179,8 +2191,6 @@ mips16_gp_pseudo_reg (void)
     {
       rtx insn, scan, after;
 
-      /* We want GCC to treat the register's value as constant, so that
-	 it can be rematerialized on demand.  */
       insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
 
       push_topmost_sequence ();
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md	2008-01-30 13:05:18.000000000 +0000
+++ gcc/config/mips/mips.md	2008-01-30 13:05:39.000000000 +0000
@@ -4265,9 +4265,9 @@ (define_insn "mfhc1<mode>"
    (set_attr "mode" "<HALFMODE>")])
 
 ;; Move a constant that satisfies CONST_GP_P into operand 0.
-(define_expand "load_const_gp"
-  [(set (match_operand 0 "register_operand" "=d")
-	(const (unspec [(const_int 0)] UNSPEC_GP)))])
+(define_expand "load_const_gp_<mode>"
+  [(set (match_operand:P 0 "register_operand" "=d")
+	(const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
 
 ;; Insn to initialize $gp for n32/n64 abicalls.  Operand 0 is the offset
 ;; of _gp from the start of this function.  Operand 1 is the incoming