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Patch for bug 33524 (SSE5 breakage)


I just noticed I had a typo in my SSE5 checkin that broke vectorized SI->DI
conversions (bug 33524).  At present, I haven't done the full bootstrap/check,
but I will (the patch is fairly obvious, and it fixes the bug).  The following
patch fixes this.  Ok to apply?

<gcc>
2007-09-21  Michael Meissner  <michael.meissner@amd.com>

	* config/i386/i386.c (ix86_expand_sse5_unpack): Fix typos in
	converting SI->DI mode.

<gcc/testsuite>
2007-09-21  Michael Meissner  <michael.meissner@amd.com>

	* sse5-convert.c: New file, test int->long vectorized conversions.

*** gcc/config/i386/i386.c.~1~	Mon Sep 17 18:07:16 2007
--- gcc/config/i386/i386.c	Fri Sep 21 16:25:45 2007
*************** ix86_expand_sse5_unpack (rtx operands[2]
*** 13561,13575 ****
        for (i = 0; i < 16; i++)
  	RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
  
!       for (i = 0; i < 4; i++)
  	RTVEC_ELT (vs, i) = GEN_INT (i + h2);
  
        p = gen_rtx_PARALLEL (VOIDmode, vs);
        x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
        if (unsigned_p)
! 	emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
        else
! 	emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
        break;
  
      default:
--- 13561,13575 ----
        for (i = 0; i < 16; i++)
  	RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
  
!       for (i = 0; i < 2; i++)
  	RTVEC_ELT (vs, i) = GEN_INT (i + h2);
  
        p = gen_rtx_PARALLEL (VOIDmode, vs);
        x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
        if (unsigned_p)
! 	emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
        else
! 	emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
        break;
  
      default:
*** gcc/testsuite/gcc.target/i386/sse5-convert.c.~1~	Fri Sep 21 16:42:48 2007
--- gcc/testsuite/gcc.target/i386/sse5-convert.c	Fri Sep 21 16:42:41 2007
***************
*** 0 ****
--- 1,24 ----
+ /* Test that the compiler properly optimizes vector SI->DI conversions.  This
+    was a bug in the initial SSE5 code.  */
+ 
+ /* { dg-do compile { target x86_64-*-*} } */
+ /* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+ 
+ typedef long long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+ 
+ #define SIZE 10240
+ union {
+   signed   int   si[SIZE];
+   signed   long  sl[SIZE];
+   __m128i        align;
+ } a, b;
+ 
+ void conv_sign_int_sign_long (void)
+ {
+   int i;
+ 
+   for (i = 0; i < SIZE; i++)
+     a.sl[i] = b.si[i];
+ }
+ 
+ /* { dg-final { scan-assembler "pperm" } } */


-- 
Michael Meissner, AMD
90 Central Street, MS 83-29, Boxborough, MA, 01719, USA
michael.meissner@amd.com



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