This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: SSE5 patches round 3
On 9/12/07, Michael Meissner <michael.meissner@amd.com> wrote:
> Ok, here is the latest version of these patches. The floating point
> multiply/add ops are now under a single UNSPEC SSE5_INTRINSIC. I tightened up
> the code for the scalar floating multiply/add intrinsic, so the upper bits
> always come from the first argument. I renamed the vec_merge functions to have
> 'vm' in them. I bootstraped and make check the patches, and got the same
> regressions. Note, I did apply Ira's patch to params.def when doing the
> bootstrap to reduce the vectorizer errors. I went back on sse-1{2,3,4}.c to
> adding -msse5 and not adding -msse4a (since that comes on by default).
*** 4998,5003 ****
--- 5626,5633 ----
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, true, true);
+ else if (TARGET_SSE5)
+ ix86_expand_sse5_unpack (operands, true, true);
else
ix86_expand_sse_unpack (operands, true, true);
DONE;
You probably want to unpack for TARGET_SSE5 first, but it is your call.
2007-09-11 Michael Meissner <michael.meissner@amd.com>
Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Tony Linthicum <tony.linthicum@amd.com>
* config/i386/i386.h (TARGET_SSE5): New macro for SSE5.
(TARGET_ROUND): New macro for the round/ptest instructions which
are shared between SSE4.1 and SSE5.
(OPTION_MASK_ISA_ROUND): Ditto.
(OPTION_ISA_ROUND): Ditto.
(TARGET_FUSED_MADD): New macro for -mfused-madd swtich.
(TARGET_CPU_CPP_BUILTINS): Add SSE5 support.
[...]
The patch is OK for mainline. If there are any other (minor) issues,
we can address them during stage3.
Thanks,
Uros.