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Re: SSE5 patches round 3
- From: "Uros Bizjak" <ubizjak at gmail dot com>
- To: "Meissner, Michael" <michael dot meissner at amd dot com>
- Cc: "GCC Patches" <gcc-patches at gcc dot gnu dot org>, "Harle, Christophe" <christophe dot harle at amd dot com>, "rajagopal, dwarak" <dwarak dot rajagopal at amd dot com>
- Date: Tue, 11 Sep 2007 10:35:41 +0200
- Subject: Re: SSE5 patches round 3
- References: <46E5ACAE.2040808@gmail.com> <6096959DEF5C9447A6BF80BDC7EB9EDC0615611C@SBOSEXMB1.amd.com>
On 9/10/07, Meissner, Michael <michael.meissner@amd.com> wrote:
> I was just being conservative, since it would be possible to have the
> register being stored to in operands[0] be used as an index/base
> register in one of the memory operations. If you load up op0 with the
> memory operand that doesn't use op0, you will get a segfault in the
> instruction when you use op0 as an index regiser. Hence checking for
> reload_completed (reload won't use op0 due to the '&' constraint), or
> the register not being mentioned (which I would anticipate happening in
> just about every code, but without doing the tests, you can't verify
> it).
In post-reload case, you don't have to check registers with
"!reg_mentioned_p", bercause (quote from the documentation):
`&'
Means (in a particular alternative) that this operand is an
"earlyclobber" operand, which is modified before the instruction is
finished using the input operands. Therefore, this operand may
not lie in a register that is used as an input operand or as part
of any memory address.
Uros.